Delta-sigma ad converter and delta-sigma ad converting method

Patent metadata

Field	Value
Publication number	US-10720939-B2
Application number	US-201916438491-A
Country	US
Kind code	B2
Filing date	Jun 12, 2019
Priority date	Jun 12, 2018
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

Provided is a delta-sigma AD converter including a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal; a digital filtering section that filters the digital signal with the oversampling ratio; a control terminal into which an external control signal is input; an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and a setting section that sets the oversampling ratio based on interval information of the external control signal.

First claim

What is claimed is:

1. A delta-sigma AD converter comprising:
a delta-sigma modulating section that outputs a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal;
a digital filtering section that filters the digital signal with the oversampling ratio;
a control terminal into which an external control signal is input;
an output control section that performs control to output an output signal based on the filtered digital signal, according to the external control signal; and
a setting section that sets the oversampling ratio based on interval information of the external control signal, wherein
the external control signal designates a start timing of a conversion cycle, and
the setting section changes a time period from the start timing to an output timing at which the output control section outputs the output signal, according to the set oversampling ratio.

2. The delta-sigma AD converter according to claim 1 , wherein
the setting section changes a filter coefficient of the digital filtering section, according to the set oversampling ratio.

3. The delta-sigma AD converter according to claim 1 , wherein
the delta-sigma modulating section includes an analog integrating section that integrates a signal that is based on the input analog signal, and
the setting section changes the number of times the analog integrating section performs the integration, according to the set oversampling ratio.

4. The delta-sigma AD converter according to claim 1 , wherein
the external control signal designates a start timing of a conversion cycle by changing from a first logic value to a second logic value, and
the setting section sets the oversampling ratio based on a length of a target interval that is an interval during which the external control signal is the first logic value, an interval during which the external control signal is the second logic value, or a total interval that includes the interval during which the external control signal is the first logic value and the interval during which the external control signal is the second logic value.

5. The delta-sigma AD converter according to claim 4 , wherein
the output control section outputs the output signal at a timing corresponding to a clock signal input thereto, and
the setting section sets the oversampling ratio based on the number of clock pulses of the clock signal in the target interval.

6. The delta-sigma AD converter according to claim 4 , wherein
the setting section sets the oversampling ratio of a following conversion cycle based on the external control signal.

7. The delta-sigma AD converter according to claim 4 , wherein
the setting section sequentially sets a number of oversampling ratios that corresponds to the length of the target interval, among a plurality of oversampling ratios, in the conversion cycle, and
the output control section sequentially outputs the output signal corresponding to the sequentially set oversampling ratios in the conversion cycle.

8. The delta-sigma AD converter according to claim 1 , wherein
the delta-sigma modulating section includes:
an analog integrating section that integrates a signal that is based on the input analog signal;
a quantizing section that quantizes an output signal of the analog integrating section;
a DA converting section that generates a feedback signal based on output of the quantizing section; and
an adding section that adds the feedback signal from the DA converting section to the input analog signal, and

the analog integrating section integrates output of the adding section.

9. The delta-sigma AD converter according to claim 8 , wherein
the delta-sigma modulating section further includes a resetting section that resets an integrated value held by the analog integrating section every conversion cycle.

10. The delta-sigma AD converter according to claim 1 , wherein
the control terminal is an input terminal for a chip select signal of an SPI (Serial Peripheral Interface).

11. A delta-sigma AD converting method comprising: outputting, by a delta-sigma AD converter, a digital signal obtained by performing delta-sigma modulation with an oversampling ratio on an input analog signal;
filtering, by the delta-sigma AD converter, the digital signal with the oversampling ratio;
performing control, by the delta-sigma AD converter, to output an output signal based on the filtered digital signal, according to an external control signal input from a control terminal, the external control signal designating a start timing of a conversion cycle;
setting, by the delta-sigma AD converter, the oversampling ratio based on interval information of the external control signal; and
changing, by the delta-sigma AD converter, a time period from the start timing to an output timing at which the output signal is output, according to the set oversampling ratio.

Assignees

• Asahi Kasei Microdevices Corp

Inventors

• Miyahara Yuichi

Classifications

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/396 Primary

  among different frequency bands · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/496 Primary

  Details of sampling arrangements or methods · CPC title