Techniques for input formatting and coefficient selection for sample rate converter in parallel implementation scheme

Patent metadata

Field	Value
Publication number	US-10720904-B2
Application number	US-201816188146-A
Country	US
Kind code	B2
Filing date	Nov 12, 2018
Priority date	Nov 12, 2018
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“F in ”) and output from the SRC at an output rate (“F out ”) equal to F in *L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*T pp input samples to the filter at a given time, wherein T pp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*T pp of the coefficients to the LPF at a given time.

First claim

What is claimed is:

1. A sample rate converter (“SRC”) for implementing a rate conversion L/M, wherein L is an upconversion factor of the SRC and M is a downconversion factor of the SRC, and wherein data is input to the SRC at an input rate (“F in ”) and output from the SRC at an output rate (“F out ”) equal to F in *L/M, the SRC comprising:
a low pass filter (“LPF”) including P filters, wherein P is a parallelization factor of the SRC;
an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing a number of input samples to the filter at a given time; and
a coefficient bank for storing a plurality of coefficients and for providing a number of the coefficients to the LPF at a given time.

2. The SRC of claim 1 , wherein the number of input samples comprises P*T pp input samples, wherein T pp is a number of taps per phase of the LPF, and wherein the input formatter receives the samples at F in and provides P*T pp input samples to the LPF at F out .

3. The SRC of claim 1 , wherein the number of the coefficients provided to the LPF at a given time comprises P*T pp of the coefficients, wherein T pp is a number of taps per phase of the LPF, and wherein the coefficient bank provides P*T pp of the coefficients to the filter at F out .

4. The SRC of claim 1 , wherein the input formatter comprises a first in first out (“FIFO”) buffer for storing the received samples at F in and first circuitry for reading N uniq ones of the stored samples from the FIFO buffer at F out .

5. The SRC of claim 4 , wherein N uniq =(P−1) * ceil(M/L) + T pp , for ceil (M/L)<T pp .

6. The SRC of claim 4 , wherein the first circuitry comprises a first multiplexer (MUX) having inputs respectively connected to outputs of the FIFO buffer and a FIFO read pointer generator for generating a select signal to the MUX.

7. The SRC of claim 6 , wherein the input formatter comprises second circuitry for selecting P*T pp of the N uniq ones of the stored samples read from the FIFO buffer in accordance with L/M to be provided to the filter as the P*T pp input samples.

8. The SRC of claim 7 , wherein the second circuitry comprises at least one second MUX having inputs selectively connected to outputs of the first MUX and a MUX pointer for generating select signals to each at least one second MUX.

9. The SRC of claim 1 , wherein each of the P filter instances implements a sum of products (“SOP”) operation on coefficients and formatted samples received thereby to generate an output sample and outputs the output sample at F out .

10. The apparatus of claim 1 , wherein the coefficient bank rearranges coefficients stored therein in accordance with:
new index ( i,j )=mod[( iP+j ) M,L ]; and
Coeff rearranged ( i,j )=Coeff original (new index ( i,j ))

where i=0 to ((L/P)−1) and j=parallel line (0 to (P−1)).

11. The apparatus of claim 10 , wherein the coefficient bank comprises P sets of L/P coefficient registers and P MUXes, wherein each one of the P sets of L/P coefficient registers is connected to input of one of the P MUXes, the coefficient bank further comprising a counter having an output connected to select inputs of each of the P MUXes, the counter having a maximum count value of (L/P)−1.

12. An apparatus comprising:
sample rate conversion circuitry (“SRC”) for implementing a rate conversion L/M, wherein L is an upconversion factor of the SRC and M is a downconversion factor of the SRC, and wherein data is input to the SRC at an input rate (“F in ”) and output from the SRC at an output rate (“F out ”) equal to F in *L/M, the SRC comprising:
a low pass filter (“LPF”) including P filter instances, wherein P is a parallelization factor of the SRC;
an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing a number of input samples to the filter at a given time, and
a coefficient bank for storing a plurality of coefficients and for providing a number of the coefficients to the LPF at a given time;

wherein the input formatter receives the samples at F in and provides the number of input samples to the LPF at F out ; and
wherein the coefficient bank provides the number of the coefficients to the filter at F out .

13. The apparatus of claim 12 , wherein the input formatter comprises:
a first in first out (“FIFO”) buffer for storing the received samples at F in ; and
read circuitry for causing N uniq ones of the stored samples to be read from the FIFO buffer at F out ;
wherein the read circuitry comprises a first multiplexer (MUX) having inputs respectively connected to outputs of the FIFO buffer and a FIFO read pointer generator for generating a select signal to the MUX.

14. The apparatus of claim 13 , wherein the input formatter comprises select circuitry for selecting P*T pp of the N uniq ones of the stored samples read from the FIFO buffer in accordance with L/M to be provided to the filter as the P*T pp input samples, wherein T pp is a number of taps per phase of the LPF, and wherein the select circuitry comprises at least one second MUX having inputs selectively connected to outputs of the first MUX and a MUX pointer generator for generating select signals to each at least one second MUX.

15. The apparatus of claim 12 , wherein the coefficient bank rearranges coefficients stored therein in accordance with a function of P, M, and L.

16. The apparatus of claim 15 , wherein the coefficient bank comprises P sets of L/P coefficient registers and P MUXes, wherein each one of the P sets of L/P coefficient registers is connected to input of one of the P MUXes, the coefficient bank further comprising a counter having an output connected to select inputs of each of the P MUXes, the counter having a maximum count value of (L/P)−1.

17. A method for performing a sample rate conversion L/M, wherein L is an upcoming factor of the SRC and M is a downconversion factor of the SRC, and wherein data wherein an input data rate is F in and an output data rate is F out and wherein F out is equal to F in *L/M, the method comprising:
receiving data samples at F in ;
storing the received data samples in a first in first out (“FIFO”) buffer;
reading N uniq ones of the stored received data samples from the FIFO buffer at F out ,
a number of the N uniq ones of the stored received data samples read from the FIFO buffer to be provided to the filter;
providing the selected number of ones of the N uniq ones of the stored received data samples read from the FIFO buffer to the filter at F out ; and
outputting a number of ones of a plurality of stored coefficients to the filter at F out .

18. The method of claim 17 , wherein the reading is performed using read circuitry comprising a first multiplexer (MUX) having inputs respectively connected to outputs of the FIFO buffer and a FIFO read pointer generator for generating a select signal to the MUX.

19. The method of claim 18 , wherein the selecting is performed by select circuitry comprising at least one second MUX having inputs selectively connected to outputs of the first MUX and a MUX pointer generator for generating select signals to each at least one second MUX.

20. The method of claim 17 further comprising rearranging the stored coefficients before the outputting in accordance with a function of P, M, and L.

Assignees

• Analog Devices Int Unlimted Company
• Analog Devices International Unlimited Co

Inventors

• Kumar Vinoth
• Pande Bhanu
• Speir Carroll C
• Rao Satishchandra G
• K Sajkapoor P

Classifications

• H03H17/0621 Primary

  with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing · CPC title

• H03H17/0685 Primary

  the ratio being rational · CPC title