Resistance circuit, oscillation circuit, and in-vehicle sensor apparatus

Patent metadata

Field	Value
Publication number	US-10720418-B2
Application number	US-201716495564-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Mar 22, 2017
Publication date	Jul 21, 2020
Grant date	Jul 21, 2020

Abstract

A resistance circuit is configured such that a P-type resistance section and an N-type resistance section are electrically connected in series, the P-type resistance section is configured with P-type diffusion layer resistance elements that are disposed to form a right angle with respect to each other and that are electrically connected in series, and the N-type resistance section is configured with N-type diffusion layer resistance elements that are disposed to form the right angle with respect to each other and that are electrically connected in series. Furthermore, the P-type diffusion layer resistance element is disposed along a <100> orientation direction of a semiconductor substrate, and the N-type diffusion layer resistance element is disposed along a <110> orientation direction of the semiconductor substrate. It is thereby possible to provide the resistance circuit, an oscillation circuit, and an in-vehicle sensor apparatus that reduce stress-induced characteristic fluctuations.

First claim

The invention claimed is:

1. A resistance circuit comprising:
a semiconductor substrate;
an N-type resistance section that is formed on a principal surface of the semiconductor substrate; and
a P-type resistance section that is formed on the principal surface of the semiconductor substrate and that is electrically connected in series to the N-type resistance section, wherein
the N-type resistance section has a first N-type diffusion layer resistance element and a second N-type diffusion layer resistance element that are disposed to form a right angle with respect to each other and that are electrically connected in series,
the P-type resistance section has a first P-type diffusion layer resistance element and a second P-type diffusion layer resistance element that are disposed to form the right angle with respect to each other and that are electrically connected in series,
the first N-type diffusion layer resistance element is disposed along a second crystal orientation direction of the semiconductor substrate, the second crystal orientation direction being different from a first crystal orientation direction of the semiconductor substrate, the first crystal orientation direction being a direction in which a stress sensitivity based on a piezoresistance coefficient becomes maximum, and
the first P-type diffusion layer resistance element is disposed along a direction different from the second crystal orientation direction.

2. The resistance circuit according to claim 1 , wherein
resistance values of the first P-type diffusion layer resistance element and the second P-type diffusion layer resistance element are larger than a resistance value of any of the first N-type diffusion layer resistance element and the second N-type diffusion layer resistance element.

3. The resistance circuit according to claim 1 , wherein
the second crystal orientation direction is a <110> orientation direction.

4. The resistance circuit according to claim 1 , wherein
the first P-type diffusion layer resistance element is disposed along an orientation direction at an angle of 45 degrees with respect to the second crystal orientation direction.

5. The resistance circuit according to claim 1 , wherein
the first P-type diffusion layer resistance element is formed from a semiconductor region where a P-type impurity is introduced into the semiconductor substrate,
a first metal interconnection layer is electrically connected to one end portion of the semiconductor region via a first silicide region,
a second metal interconnection layer is electrically connected to another end portion of the semiconductor region via a second silicide region,
one side of the first silicide region, the one side being opposed to the second silicide region, is provided along a direction orthogonal to a direction in which the first P-type diffusion layer resistance element extends, and
one side of the second silicide region, the one side being opposed to the first silicide region, is provided along the direction orthogonal to the direction in which the first P-type diffusion layer resistance element extends.

6. The resistance circuit according to claim 5 , wherein
a first insulating film is formed between the first silicide region and the first metal interconnection layer,
a second insulating film is formed between the second silicide region and the second metal interconnection layer,
a plurality of first contacts electrically connecting the first silicide region to the first metal interconnection layer are formed in the first insulating film in parallel to the one side of the first silicide region, the one side being opposed to the second silicide region, and
a plurality of second contacts electrically connecting the second silicide region to the second metal interconnection layer are formed in the second insulating film in parallel to the one side of the second silicide region, the one side being opposed to the first silicide region.

7. The resistance circuit according to claim 1 , wherein
the N-type resistance section and the P-type resistance section are alternately disposed in the second crystal orientation direction and alternately disposed in a direction orthogonal to the second crystal orientation direction.

8. The resistance circuit according to claim 1 , wherein
the N-type resistance section further has a third N-type diffusion layer resistance element and a fourth N-type diffusion layer resistance element that are disposed to form the right angle with respect to each other and that are electrically connected in series,
the P-type resistance section further has a third P-type diffusion layer resistance element and a fourth P-type diffusion layer resistance element that are disposed to form the right angle with respect to each other and that are electrically connected in series,
lengths of the third N-type diffusion layer resistance element and the fourth N-type diffusion layer resistance element in an extension direction are smaller than a length of any of the first N-type diffusion layer resistance element and the second N-type diffusion layer resistance element in the extension direction, and
lengths of the third P-type diffusion layer resistance element and the fourth P-type diffusion layer resistance element in an extension direction are smaller than a length of any of the first P-type diffusion layer resistance element and the second P-type diffusion layer resistance element in the extension direction.

9. The resistance circuit according to claim 1 , including:
a first N-type region that is formed on the principal surface of the semiconductor substrate; and
a second N-type region that is formed on the principal surface of the semiconductor substrate to be apart from the first N-type region, wherein
the first P-type diffusion layer resistance element is formed within the first N-type region,
the second P-type diffusion layer resistance element is formed within the second N-type region,
the first N-type region functions as the first N-type diffusion layer resistance element, and
the second N-type region functions as the second N-type diffusion layer resistance element.

10. The resistance circuit according to claim 1 , wherein
the first P-type diffusion layer resistance element is configured with a first part and a second part provided to be apart from each other in the second crystal orientation direction,
the first part and the second part are disposed in a direction different from the second crystal orientation direction, and
the first part and the second part are electrically connected in parallel.

11. The resistance circuit according to claim 1 , wherein
an aspect ratio of the first P-type diffusion layer resistance element is equal to or higher than two.

12. An oscillation circuit comprising:
a semiconductor substrate;
a capacitor that is formed on a principal surface of the semiconductor substrate; and
a resistance circuit that is formed on the principal surface of the semiconductor substrate,
an oscillating frequency of the oscillation circuit being set by a capacitance value of the capacitor and a resistance value of the resistance circuit, wherein
the resistance circuit includes:
an N-type resistance section that is formed on the principal surface of the semiconductor substrate; and
a P-type resistance section that is formed on the principal surface of the semiconductor substrate and that is electrically connected in series to the N-type resistance section,
the N-type resistance section has a first N-type diffusion layer resistance element and a second N-type diffusion layer resistance element that are disposed to form a right angle with respect to

Assignees

• Hitachi Automotive Systems Ltd

Inventors

• Yanagawa Yoshimitsu
• Nara Yoshikazu
• Matsumoto Masahiro
• Nakano Hiroshi
• Kotabe Akira

Classifications

• H10D84/209

  of only resistors · CPC title

• H10D1/47 Primary

  Resistors having no potential barriers · CPC title

• H10D1/43

  Resistors having PN junctions · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title