Digital phase shifter switch and transmission line reduction

Patent metadata

Field	Value
Publication number	US-10714830-B2
Application number	US-201715723692-A
Country	US
Kind code	B2
Filing date	Oct 3, 2017
Priority date	Oct 3, 2017
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

A digital phase shifter is described where each bit of the phase shifter has a circuit block including one PIN diode in parallel with one transmission line. The phase shifter requires only one PIN diode and one transmission line per bit circuit block. Each PIN diode behaves like a simple switch for phase shifting. When the PIN diode is forward biased (“on” state), current flows through the PIN diode and the RF signal is not phase shifted. When the pin diode is not forward biased (“off” state), current flows through the transmission line parallel to the PIN diode and the RF signal is phase shifted by the transmission line. The digital phase shifter may have n circuit blocks in series, and adjacent PIN diodes may share a current when both are on. The phase shifter may be implemented in a phased array or reflect array antenna including multiple phase shifters.

First claim

What is claimed is:

1. A phase shifter, comprising:
first circuitry corresponding to a first bit of the phase shifter, the first circuitry comprising:
a first PIN diode;
a first transmission line parallel to the first PIN diode, wherein the first transmission line is configured to phase shift a radio frequency (RF) signal that passes through the first transmission line; and
a first biasing circuit configured to forward bias or reverse bias the first PIN diode, wherein an RF signal received at the phase shifter passes through the first PIN diode when the first PIN diode is under forward bias, and wherein the RF signal received at the phase shifter passes through the first transmission line when the first PIN diode is not under forward bias.

2. The phase shifter of claim 1 , further comprising:
second circuitry in series with the first circuitry, wherein the second circuitry corresponds to a second bit of the phase shifter, wherein the second circuitry comprises:
a second PIN diode;
a second transmission line parallel to the second PIN diode, wherein the second transmission line is configured to phase shift an RF signal that passes through the second transmission line; and
a second biasing circuit configured to forward bias or reverse bias the second PIN diode, wherein the RF signal received at the phase shifter passes through the second PIN diode when the second PIN diode is forward biased, and wherein the RF signal received at the phase shifter passes through the second transmission line when the second PIN diode is not forward biased.

3. The phase shifter of claim 2 , wherein the first biasing circuit is configured to forward bias the second PIN diode when both the first PIN diode and the second PIN diode are forward biased, and wherein the second biasing circuit is configured to forward bias the second PIN diode when the first PIN diode is not forward biased.

4. The phase shifter of claim 2 , wherein the phase shifter is an n-bit phase shifter where n≥2, and wherein a number of transmission lines in the phase shifter is equal to n.

5. The phase shifter of claim 4 , wherein a number of PIN diodes in the phase shifter is equal to n.

6. The phase shifter of claim 4 , wherein n≥4.

7. The phase shifter of claim 1 , wherein the first biasing circuit comprises: a direct current voltage source configured to apply a constant voltage for generating a forward or reverse bias on the first PIN diode.

8. The phase shifter of claim 7 , wherein the first biasing circuit further comprises: an inductor configured to block RF signals from entering the first biasing circuit.

9. The phase shifter of claim 8 , wherein the first biasing circuit, further comprises: a bypass capacitor configured to reduce AC noise present on a DC signal generated at the first biasing circuit.

10. The phase shifter of claim 1 , further comprising:
an input RF port and an output RF port;
a first direct current blocking capacitor configured to block DC bias from flowing into the input RF port; and
a second direct current blocking capacitor configured to block DC bias from flowing into the output RF port.

11. An antenna, comprising:
a plurality of quantized phase shifters, each of the plurality of quantized phase shifters comprising a first circuit block corresponding to a first bit of the quantized phase shifter, the first circuit block comprising:
a transmission line configured to phase shift a radio frequency (RF) signal that passes through the transmission line;
a PIN diode in parallel with the transmission line; and
a biasing circuit configured to forward bias or reverse bias the PIN diode, wherein an RF signal received at the quantized phase shifter passes through the PIN diode when the PIN diode is under forward bias, and wherein the RF signal received at the phase shifter passes through the transmission line when the PIN diode is not under forward bias; and

a plurality of antenna elements, wherein each of the plurality of antenna elements is configured to receive a phase shifted signal from a respective one of the plurality of quantized phase shifters.

12. The antenna of claim 11 , wherein each of the plurality of quantized phase shifters is an n-bit phase shifter where n≥2, and wherein each of the plurality of quantized phase shifters comprises n circuit blocks, wherein each of the n circuit blocks comprises a PIN diode in parallel with a transmission line configured to phase shift an RF signal that passes through the transmission line.

13. The antenna of claim 12 , wherein for each of the plurality of quantized phase shifters, the n circuit blocks are in series.

14. The antenna of claim 13 , wherein each of the plurality of quantized phase shifters comprises n transmission lines and n PIN diodes.

15. The antenna of claim 11 , wherein each of the biasing circuits comprises:
a direct current voltage source configured to apply a constant voltage for generating a forward bias or reverse bias on the PIN diode; and
an inductor configured to block RF signals from entering the biasing circuit.

16. The antenna of claim 11 , wherein the antenna is a phased array or reflect array antenna.

17. A method, comprising:
receiving a first radio frequency (RF) signal at an input RF port of a quantized phase shifter, wherein the quantized phase shifter comprises first circuitry corresponding to a first bit of the quantized phase shifter, the first circuitry comprising: a first PIN diode in parallel to a first transmission line configured to phase shift an input RF signal that passes through the first transmission line;
forwarding biasing the first PIN diode; and
after forward biasing the first PIN diode, passing the first RF signal through the first PIN diode and not the first transmission line.

18. The method of claim 17 , further comprising:
receiving a second RF signal at the input RF port;
reverse biasing the first PIN diode; and
after reverse biasing the first PIN diode, passing the second RF signal through the first transmission line and not the first PIN diode.

19. The method of claim 17 , wherein the quantized phase shifter comprises second circuitry in series with the first circuitry, the second circuitry corresponding to a second bit of the quantized phase shifter, wherein the second circuitry comprises a second PIN diode in parallel to a second transmission line configured to phase shift an input RF signal that passes through the second transmission line, wherein the method further comprises:
forward biasing the second PIN diode; and
after forward biasing the second PIN diode, passing the first RF signal through the second PIN diode and not the second transmission line.

20. The method of claim 19 , wherein the first PIN diode and the second PIN diode are forward biased using the same current.

Assignees

• Hughes Network Systems Llc

Inventors

• Jackson Thomas
• Lu Bingqian
• Alsawaha Hamad
• Hou Peter
• Mao Yilin

Classifications

• H01P1/185

  using a diode or a gas filled discharge tube · CPC title

• H03H7/20

  Two-port phase shifters providing an adjustable phase shift · CPC title

• H03H7/185

  comprising distributed impedance elements together with lumped impedance elements · CPC title

• H01Q3/38 Primary

  the phase-shifters being digital · CPC title