Semiconductor device

Patent metadata

Field	Value
Publication number	US-10714606-B2
Application number	US-201615753342-A
Country	US
Kind code	B2
Filing date	Sep 5, 2016
Priority date	Sep 22, 2015
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm−2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a rear electrode that is grounded;
a conductive substrate that is disposed on a surface of the rear electrode and that has a ground potential;
a channel forming layer that is located above the conductive substrate and includes at least one hetero-junction structure, the hetero-junction structure including a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer;
a first electrode that is in contact with the second GaN-type semiconductor layer;
a second electrode that is in contact with the second GaN-type semiconductor layer and is located separately from the first electrode;
a third electrode that is in contact with the second GaN-type layer;
an electrical field easing layer that is formed of a GaN-type semiconductor layer and is located between the first electrode and the second electrode above the second GaN-type semiconductor layer; and
a fourth electrode that is located above the electrical field easing layer, wherein
the first electrode, the second electrode, the third electrode, and the fourth electrode provide four terminals,
the first electrode corresponds to a gate electrode, the second electrode corresponds to a drain electrode, and the third electrode corresponds to a source electrode,
the third electrode, the fourth electrode, and the rear electrode have the ground potential,
a distance between the first electrode and the second electrode is greater than a thickness of the hetero-junction structure including the first GaN-type semiconductor layer and the second GaN-type semiconductor layer,
a distance between the fourth electrode and the second electrode is greater than the thickness of the hetero-junction structure,
the channel forming layer is configured to generate a current by a carrier of a 2-dimensional electron gas, the 2-dimensional electron gas being generated by a polarization in the first GaN-type semiconductor layer adjacent to an interface between the first GaN-type semiconductor layer and the second GaN-type semiconductor layer,
a total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×10 13 to 1.5×10 13 cm −2 , and
the charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer.

2. The semiconductor device according to claim 1 , further comprising
the fourth electrode that is located between the first electrode and the second electrode above the second GaN-type semiconductor layer, wherein
the fourth electrode includes a Schottky electrode that has an electrical potential equivalent to the third electrode, and
the first electrode, the second electrode, the third electrode and the fourth electrode provide four terminals.

3. The semiconductor device according to claim 1 , wherein
the electrical field easing layer is formed of an i-type GaN layer or a p-type GaN layer.

4. The semiconductor device according to claim 3 , wherein
the electrical field easing layer has a protruding portion protruding toward the second electrode from an end of the fourth electrode closest to the second electrode, and
the protruding portion has a length equal to or less than a half of a distance between the fourth electrode and the second electrode.

5. The semiconductor device according to claim 1 , wherein
the gate electrode is included in a gate electrode structure provided by a Schottky electrode structure in which the first electrode, which provides the gate electrode, includes a Schottky electrode that is in contact with the second GaN-type semiconductor layer.

6. The semiconductor device according to claim 1 , further comprising
a gate insulation film that is located above the second GaN-type semiconductor layer, wherein
the gate electrode is included in a gate electrode structure provided by a MOS structure in which the first electrode, which provides the gate electrode, is disposed on the second GaN-type semiconductor layer through the gate insulation film.

7. The semiconductor device according to claim 1 , further comprising
a gate GaN layer that is formed of a GaN-type semiconductor and is located above the second GaN-type semiconductor layer, wherein
the gate electrode is included in a gate electrode structure provided by a structure in which the first electrode, which provides the gate electrode, is disposed on the second GaN-type semiconductor layer through the gate GaN layer.

8. The semiconductor device according to claim 1 , further comprising
a charge adjusting layer that is located above the second GaN-type semiconductor layer and is configured to increase the total fixed charge quantity in the drift region.

9. The semiconductor device according to claim 8 , wherein
the charge adjusting layer is formed of an n-type AlGaN layer or an n-type GaN layer, and
the charge adjusting layer is configured to generate fixed charges by n-doping.

10. The semiconductor device according to claim 1 , wherein
the total fixed charge quantity corresponds to a total number of charges included in the first GaN-type semiconductor layer and the second GaN-type semiconductor layer.

11. The semiconductor device according to claim 1 , wherein
the total fixed charge quantity, which is from 0.5×10 13 to 1.5×10 13 cm −2 , depends on a concentration of the 2-dimensional electron gas, and
the concentration of the 2-dimensional electron gas depends on an Al mixed crystal ratio and a thickness of the second GaN-type semiconductor layer.

12. The semiconductor device according to claim 1 , wherein
the first electrode is disposed on the second GaN-type semiconductor layer through an insulating film; and
a surface of the second GaN-type semiconductor layer is partially recessed to provide a recess at a position where the first electrode is formed.

13. The semiconductor device according to claim 1 , wherein
a length of the electrical field easing layer from the fourth electrode to an edge of the electrical field easing layer in a direction toward the second electrode is equal to, or less than, one half of the distance between the fourth electrode and the second electrode.

Assignees

• Denso Corp

Inventors

• Eum Youngshin
• Oyama Kazuhiro
• Higuchi Yasushi
• Tsuchiya Yoshinori
• Hoshi Shinichi

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title