Driving circuit, method for controlling light emission and display device

Patent metadata

Field	Value
Publication number	US-10714053-B2
Application number	US-201816191495-A
Country	US
Kind code	B2
Filing date	Nov 15, 2018
Priority date	Apr 19, 2018
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

The present disclosure provides a driving circuit, a method for controlling light emission, and a display device. The driving circuit includes one or more light emission shift registers, each of which includes a first processing module configured to control a signal at a first node based on signals at the input signal terminal, the first clock signal terminal and the second clock signal terminal; a second processing module including first and second transistors, wherein the first transistor is a dual-gate transistor, and the second transistor has a first terminal electrically connected to the pulse signal terminal and a second terminal electrically connected to the second node; and an output module configured to control a signal at an output signal terminal based on the signals at the first level signal terminal, the second level signal terminal, the first node and the second node.

First claim

What is claimed is:

1. A driving circuit, comprising one or more light emission shift registers, wherein each of the one or more light emission shift registers comprises:
a first processing module electrically connected to an input signal terminal, a first clock signal terminal and a second clock signal terminal, and configured to control a signal at a first node based on a signal at the input signal terminal, a signal at the first clock signal terminal and a signal at the second clock signal terminal;
a second processing module electrically connected to a first level signal terminal, the first clock signal terminal, the second clock signal terminal, a pulse signal terminal and the first node, and configured to control a signal at a second node based on a signal at the first level signal terminal, the signal at the first clock signal terminal, the signal at the second clock signal terminal, a signal at the pulse signal terminal and the signal at the first node, wherein the second processing module comprises a first transistor and a second transistor, the first transistor is a dual-gate transistor having a control terminal electrically connected to the first node, a first terminal electrically connected to the first clock signal terminal and a second terminal electrically connected to a third node, and the second transistor has a control terminal electrically connected to the first node or the first clock signal terminal, a first terminal electrically connected to the pulse signal terminal and a second terminal electrically connected to the second node; and
an output module electrically connected to the first level signal terminal, a second level signal terminal, the first node and the second node, and configured to control a signal at an output signal terminal based on the signal at the first level signal terminal, a signal at the second level signal terminal, the signal at the first node and the signal at the second node,
wherein the first processing module comprises a third transistor, a fourth transistor, a fifth transistor, and a first capacitor,
the third transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the input signal terminal, and a second terminal electrically connected to the first node;
the fourth transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the first node, and a second terminal;
the fifth transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the second terminal of the fourth transistor, and a second terminal electrically connected to the input signal terminal or the first clock signal terminal; and
the first capacitor has a first terminal electrically connected to the first node, and a second terminal electrically connected to the second clock signal terminal.

2. The driving circuit according to claim 1 , wherein the signal at the first level signal terminal is different from the signal at the second level signal terminal; the signal at the first clock signal terminal and the signal at the second clock signal terminal are both pulse signals, the signal at the second clock signal terminal is at a high level when the signal at the first clock signal terminal is at a low level, and the signal at the first clock signal terminal is at a high level when the signal at the second clock signal terminal is at a low level.

3. The driving circuit according to claim 1 , wherein the signal at the pulse signal terminal is equal to the signal at the second clock signal terminal, and the control terminal of the second transistor is connected to the first clock signal terminal.

4. The driving circuit according to claim 3 , wherein the second processing module further comprises a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor;
the sixth transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the first level signal terminal, and a second terminal electrically connected to the third node;
the seventh transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the second clock signal terminal, and a second terminal electrically connected to a fourth node;
the eighth transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the fourth node, and a second terminal electrically connected to the second node;
the second capacitor has a first terminal electrically connected to the third node, and a second terminal electrically connected to the fourth node; and
the third capacitor has a first terminal electrically connected to a fixed level signal terminal, and a second terminal electrically connected to the second node.

5. The driving circuit according to claim 4 , wherein the second processing module further comprises a ninth transistor having a control terminal electrically connected to the input signal terminal, a first terminal electrically connected to the second clock signal terminal and a second terminal electrically connected to the first terminal of the second transistor.

6. The driving circuit according to claim 1 , wherein the signal at the pulse signal terminal is equal to a signal at a scan signal output terminal of a scan shift register, and the control terminal of the second transistor is connected to the first node;
in a case of the signal at the input signal terminal being at a high level, the signal at the first clock signal terminal being at a high level, and the signal at the second clock signal terminal being at a low level, the signal at the scan signal output terminal of the scan shift register is at a low level.

7. The driving circuit according to claim 6 , wherein the second processing module further comprises a sixth transistor, a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor;
the sixth transistor has a control terminal electrically connected to the first clock signal terminal, a first terminal electrically connected to the first level signal terminal, and a second terminal electrically connected to the third node;
the seventh transistor has a control terminal electrically connected to the third node, a first terminal electrically connected to the second clock signal terminal, and a second terminal electrically connected to a fourth node;
the eighth transistor has a control terminal electrically connected to the second clock signal terminal, a first terminal electrically connected to the fourth node, and a second terminal electrically connected to the second node;
the second capacitor has a first terminal electrically connected to the third node, and a second terminal electrically connected to the fourth node; and
the third capacitor has a first terminal electrically connected to a fixed level signal terminal, and a second terminal electrically connected to the second node.

8. The driving circuit according to claim 1 , wherein the output module comprises a tenth transistor and an eleventh transistor;
the tenth transistor has a control terminal electrically connected to the first node, a first terminal electrically connected to the first level signal terminal, and a second terminal electrically connected to the output signal terminal; and
the eleventh transistor has a control terminal electrically connected to the second node, a first terminal electrically connected to the second level signal terminal, and a second terminal electrically connected to the output signal terminal.

Assignees

• Shanghai Tianma Am Oled Co Ltd

Inventors

• Zhu Renyuan
• Li Yue
• Xiang Dongxu
• Gao Yana
• Zhou Xingyao
• Huang Gaojun
• Xu Yilin
• Cai Zhonglan
• Zhu Juan

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/2074

  using sub-pixels · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title