Display device

Patent metadata

Field	Value
Publication number	US-10714031-B2
Application number	US-201816190565-A
Country	US
Kind code	B2
Filing date	Nov 14, 2018
Priority date	Nov 28, 2017
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

A display device comprising: a display portion that is provided on a thin-film transistor (TFT) substrate and that comprises pixel capacitors and pixel transistors included in a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, a plurality of scan lines each coupled to some of the pixels arranged in the first direction, and a plurality of video signal lines each coupled to some of the pixels arranged in the second direction; and a driver that is provided on the TFT substrate and that is configured to supply video signals to the video signal lines and to control the pixel transistors to be on and off through the scan lines.

First claim

What is claimed is:

1. A display device comprising:
a display portion that is provided on a thin-film transistor (TFT) substrate and that comprises pixel capacitors and pixel transistors included in a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, a plurality of scan lines each coupled to some of the pixels arranged in the first direction, and a plurality of video signal lines each coupled to some of the pixels arranged in the second direction; and
a driver that is provided on the TFT substrate and that is configured to supply video signals to the video signal lines and to control the pixel transistors to be on and off through the scan lines, wherein
the pixel transistors comprise:
first pixel transistors that are p-channel metal-oxide semiconductor (PMOS) transistors coupled between the video signal lines and the pixel capacitors; and
second pixel transistors that are n-channel metal-oxide semiconductor (NMOS) transistors coupled in parallel to the first pixel transistors,
the scan lines comprise:
first scan lines coupled to gates of the first pixel transistors; and
second scan lines coupled to gates of the second pixel transistors, and
the driver comprises:
a first shift register configured to generate first scan signals to be sequentially supplied to the first scan lines at intervals of a predetermined period; and
a second shift register configured to generate second scan signals to be sequentially supplied to the second scan lines at intervals of the predetermined period, wherein
each of the first pixel transistors is provided by coupling a plurality of PMOS transistors in series between corresponding one of the video signal lines and corresponding one of the pixel capacitors, and
each of the second pixel transistors is provided by coupling the same number of NMOS transistors as that of the PMOS transistors included in the first pixel transistor in series between the video signal line and the pixel capacitor.

2. A display device comprising:
a display portion that is provided on a thin-film transistor (TFT) substrate and that comprises pixel capacitors and pixel transistors included in a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, a plurality of scan lines each coupled to some of the pixels arranged in the first direction, and a plurality of video signal lines each coupled to some of the pixels arranged in the second direction; and
a driver that is provided on the TFT substrate and that is configured to supply video signals to the video signal lines and to control the pixel transistors to be on and off through the scan lines, wherein
the pixel transistors comprise:
first pixel transistors that are p-channel metal-oxide semiconductor (PMOS) transistors coupled between the video signal lines and the pixel capacitors; and
second pixel transistors that are n-channel metal-oxide semiconductor (NMOS) transistors coupled in parallel to the first pixel transistors,
the scan lines comprise:
first scan lines coupled to gates of the first pixel transistors; and
second scan lines coupled to gates of the second pixel transistors, and
the driver comprises:
a first shift register configured to generate first scan signals to be sequentially supplied to the first scan lines at intervals of a predetermined period; and
a second shift register configured to generate second scan signals to be sequentially supplied to the second scan lines at intervals of the predetermined period, wherein
a high potential of the first scan signals is higher than a voltage upper limit value of the video signals supplied to the video signal lines,
a low potential of the first scan signals is equal to or lower than a middle value of a potential difference between a voltage upper limit value and a voltage lower limit value of the video signals supplied to the video signal lines,
a low potential of the second scan signals is lower than the voltage lower limit value of the video signals supplied to the video signal lines, and
a high potential of the second scan signals is equal to or higher than the middle value of the potential difference between the voltage upper limit value and the voltage lower limit value of the video signals supplied to the video signal lines.

3. A display device comprising:
a display portion that is provided on a thin-film transistor (TFT) substrate and that comprises pixel capacitors and pixel transistors included in a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, a plurality of scan lines each coupled to some of the pixels arranged in the first direction, and a plurality of video signal lines each coupled to some of the pixels arranged in the second direction; and
a driver that is provided on the TFT substrate and that is configured to supply video signals to the video signal lines and to control the pixel transistors to be on and off through the scan lines, wherein
the pixel transistors comprise:
first pixel transistors that are p-channel metal-oxide semiconductor (PMOS) transistors coupled between the video signal lines and the pixel capacitors; and
second pixel transistors that are n-channel metal-oxide semiconductor (NMOS) transistors coupled in parallel to the first pixel transistors,
the scan lines comprise:
first scan lines coupled to gates of the first pixel transistors; and
second scan lines coupled to gates of the second pixel transistors, and
the driver comprises:
a first shift register configured to generate first scan signals to be sequentially supplied to the first scan lines at intervals of a predetermined period; and
a second shift register configured to generate second scan signals to be sequentially supplied to the second scan lines at intervals of the predetermined period, wherein
the first shift register is supplied with a first positive potential higher than a voltage upper limit value of the video signals supplied to the video signal lines and with a ground (GND) potential of the display portion, and
the second shift register is supplied with a negative potential lower than a voltage lower limit value of the video signals supplied to the video signal lines and with a second positive potential lower than the first positive potential.

4. The display device according to claim 3 , wherein the first shift register and the second shift register are provided in a bezel area outside the display portion.

5. The display device according to claim 4 , wherein the first shift register and the second shift register are provided in the bezel area on either one side in the first direction.

6. The display device according to claim 4 , wherein the first shift registers and the second shift registers are provided in the bezel area on both sides in the first direction.

7. The display device according to claim 6 , wherein
the first scan lines are supplied with the first scan signals from both the first shift registers provided in the bezel area on both sides in the first direction, and
the second scan lines are supplied with the second scan signals from both the second shift registers provided in the bezel area on both sides in the first direction.

8. The display device according to claim 3 , wherein
the first shift register is provided in the bezel area on one side in the first direction, and
the second shift register is provided in the bezel area on another side in the first direction.

9. The display device according to claim 3 , wherein
some of the first scan lines coupled to the gates of the first pixel transistors of some of the pixels arranged in (b+2×c×a)th rows (where

Assignees

• Japan Display Inc

Inventors

• Hayashi Hirotaka

Classifications

• G09G3/344 Primary

  based on particles moving in a fluid or in a gas, e.g. electrophoretic devices (electrophoretic devices per se G02F1/167) · CPC title

• G02F1/136245

  having complementary transistors · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title