Separate cores to secure processes from speculative rogue cache loads

Patent metadata

Field	Value
Publication number	US-10713353-B2
Application number	US-201816016254-A
Country	US
Kind code	B2
Filing date	Jun 22, 2018
Priority date	Feb 6, 2018
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

The present disclosure addresses the meltdown vulnerability resulting from speculative execution in a multi-core processing system. The operating system (OS) can be loaded for execution on one of several processing cores (OS core), while an application can be loaded for execution on another of the processing cores (application core). The OS core uses process page tables that map the entire kernel address space to physical memory. Conversely, the application core uses pages tables that map only a portion of the kernel address space to physical memory.

First claim

The invention claimed is:

1. A method for executing an application on a computing system, the method comprising:
executing an operating system (OS) on a first processing core selected from among a plurality of processing cores in the computing system;
translating virtual addresses in a first virtual address space of an application received from the first processing core using a first set of page tables that maps an entire user address space of the application and an entire kernel address space of the OS to a physical memory shared by the plurality of processing cores;
executing the application on a second processing core selected from among the plurality of processing cores in the computing system; and
translating virtual addresses in a second virtual address space of the application received from the second processing core using a second set of page tables that maps the entire user address space of the application and at most only a portion of the kernel address space of the OS to the physical memory.

2. The method of claim 1 , wherein the first processing core always uses the first set of process page tables when translating virtual addresses in the first virtual address space of the application.

3. The method of claim 1 , wherein the second processing core always uses the second set of process page tables when translating virtual addresses in the second virtual address space of the application.

4. The method of claim 1 , wherein the application is a 64-bit application.

5. The method of claim 1 , wherein the first and second processing cores are based on a 64-bit architecture.

6. The method of claim 1 , further comprising switching execution from the second processing core to the first processing core in response to occurrence of an interrupt or an exception in the second processing core, and handling the interrupt or exception by the OS that is executing in the first processing core.

7. The method of claim 6 , further comprising the OS accessing the kernel address space using the first set of page tables.

8. The method of claim 6 , further comprising sending a message from the second processing core to the first processing core in response to a system call made by the application on the second processing core and handling the system call in the first processing core.

9. A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer device, cause the computer device to:
execute an operating system (OS) on a first processing core selected from among a plurality of processing cores comprising the computer device;
translate virtual addresses in a first virtual address space of an application received from the first processing core using a first set of page tables that maps an entire user address space of the application and an entire kernel address space of the OS to a physical memory shared by the plurality of processing cores;
execute the application on a second processing core selected from among the plurality of processing cores comprising the computer device; and
translate virtual addresses in a second virtual address space of the application received from the second processing core using a second set of page tables that maps the entire user address space of the application and at most only a portion of the kernel address space of the OS to the physical memory.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the first processing core always uses the first set of process page tables when translating virtual addresses in the first virtual address space of the application.

11. The non-transitory computer-readable storage medium of claim 9 , wherein the second processing core always uses the second set of process page tables when translating virtual addresses in the second virtual address space of the application.

12. The non-transitory computer-readable storage medium of claim 9 , wherein the computer executable instructions, which when executed by the computer device, further cause the computer device to switch execution from the second processing core to the first processing core in response to occurrence of an interrupt or an exception in the second processing core, and handle the interrupt or exception by the OS that is executing in the first processing core.

13. The non-transitory computer-readable storage medium of claim 12 , further comprising the OS accessing the kernel address space using the first set of page tables.

14. The non-transitory computer-readable storage medium of claim 12 , wherein the computer executable instructions, which when executed by the computer device, further cause the computer device to switch execution from the second processing core to the first processing core in response to a system call made by the application on the second processing core and handle the system call in the first processing core.

15. A computer apparatus comprising:
a plurality of processing cores;
a physical memory shared by the plurality of processing cores; and
a computer-readable storage medium comprising instructions for controlling the target processor to be operable to:
execute an operating system (OS) on a first processing core selected from among a plurality of processing cores;
translate virtual addresses in a first virtual address space of an application received from the first processing core using a first set of page tables that maps an entire user address space of the application and an entire kernel address space of the OS to the physical memory;
execute the application on a second processing core selected from among the plurality of processing cores; and
translate virtual addresses in a second virtual address space of the application received from the second processing core using a second set of page tables that maps the entire user address space of the application and at most only a portion of the kernel address space of the OS to the physical memory.

16. The apparatus of claim 15 , wherein the first processing core always uses the first set of process page tables when translating virtual addresses in the first virtual address space of the application.

17. The apparatus of claim 15 , wherein second processing core always uses the second set of process page tables when translating virtual addresses in the second virtual address space of the application.

18. The apparatus of claim 15 , wherein the computer-readable storage medium further comprises instructions for controlling the target processor to be operable to switch execution from the second processing core to the first processing core in response to occurrence of an interrupt or an exception in the second processing core, and handle the interrupt or exception by the OS that is executing in the first processing core.

19. The apparatus of claim 18 , further comprising the OS accessing the kernel address space using the first set of page tables.

20. The apparatus of claim 18 , wherein the computer-readable storage medium further comprises instructions for controlling the target processor to be operable to switch execution from the second processing core to the first processing core in response to a system call made by the application on the second processing core and handle the system call in the first processing core.

Assignees

• Vmware Inc

Inventors

• Wei Michael
• Tsafrir Dan
• Amit Nadav

Classifications

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/1441

  for a range · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title