Fast unaligned memory access

Patent metadata

Field	Value
Publication number	US-10713047-B2
Application number	US-201916434066-A
Country	US
Kind code	B2
Filing date	Jun 6, 2019
Priority date	Oct 21, 2011
Publication date	Jul 14, 2020
Grant date	Jul 14, 2020

Abstract

Fast unaligned memory access. hi accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.

First claim

What is claimed is:

1. A device comprising:
a load queue memory structure configured to store a load operation in a load queue entry in one of a plurality of load queue entries, each of the plurality of load queue entries including an address field, a data field and at least one field to identify a position in the address field where a misalignment of an address in the address field occurs relative to read boundaries of the device.

2. The computing device of claim 1 wherein the at least one field is configured store a first partial sum group for the load operation that provides an incremented value of an unaligned portion of the address.

3. The computing device of claim 2 wherein the at least one field of the load queue entry is configured to store a second partial sum group for the load operation that is a set of bits in the unaligned portion of the address in which a carry propagation stops to generate an aligned address from the address.

4. The computing device of claim 1 , further comprising:
a gate driven by a comparison of an aligned store address and an aligned address derived from the address field.

5. The computing device of claim 4 , wherein the gate selects a source of a load from a store queue entry and a data cache.

6. The computing device of claim 1 wherein the load queue memory structure is configured to indicate data forwarding of an aligned address component from the store queue memory structure to the load queue memory structure.

7. The computing device of claim 1 wherein the load queue memory structure is configured to indicate data forwarding of an unaligned address component from a store queue memory structure to the load queue memory structure.

8. A processor with an out of order pipeline comprising:
a store queue to store a set of store operations to be retired, at least one storage entry to store an operation, the at least one storage entry to store an unaligned address and address descriptors, the address descriptors including a set of bits of a group in the unaligned address in which a carry propagation stops to generate an aligned address from the unaligned address;
a load queue coupled to the store queue, the load queue to store a set of load operations to be retired; and
a comparison circuit coupled to the store queue and load queue configured to compare an unaligned address in at least one store queue entry to a load queue address in a single full address comparison.

9. The processor of claim 8 , wherein the comparison circuit Is configured to compare the address descriptors in the at least one storage entry with load queue address descriptors in parallel with the comparison of the unaligned address.

10. The processor of claim 9 wherein the comparison circuit is further configured to identify a match among corresponding address descriptors in the load queue and the store queue.

11. The processor of claim 10 , wherein the comparison circuit is configured to increment a full address in the at least one storage entry responsive to the match.

12. The processor of claim 9 wherein the comparison circuit is further configured to compare the address descriptors with compares of fewer bits than comprise a full address for a computer system of the processor.

13. The processor of claim 8 , wherein the comparison circuit generates a next address for the unaligned address faster than an increment operation performed by a full adder.

14. A computing device comprising:
a data cache to store instructions;
a processor coupled to the data cache to execute the instructions, the processor including a pipeline with a load queue memory structure configured to queue load operations, and
wherein said load queue memory structure is further configured to store unaligned addresses in a single line of said load queue memory structure along with a location of an unaligned address component in the unaligned address, where an unaligned address is an address that is not aligned with a read boundary of a memory of the computing device.

15. The computing device of claim 14 further configured so that only one address for the unaligned address is stored in the single line of the load queue memory structure.

16. The computing device of claim 14 further comprising a store queue memory structure configured to queue store operations.

17. The computing device of claim 16 wherein said store queue memory structure is further configured to store unaligned addresses in a single line of said load queue memory structure.

18. The computing device of claim 17 further configured so that only one address for the unaligned address is stored in said single line of said store queue memory structure.

19. The computing device of claim 18 wherein said load queue memory structure further comprises memory configured to indicate data forwarding of an aligned address component from the store queue memory structure to the load queue memory structure.

20. The computing device of claim 19 wherein the load queue memory structure further comprises memory configured to indicate data forwarding of an unaligned address component from the store queue memory structure to the load queue memory structure.

Assignees

• Intel Corp

Inventors

• Singh Mandeep
• Abdallah Mohammad

Classifications

• G06F9/34 Primary

  Addressing or accessing the instruction operand or the result {; Formation of operand address; Addressing modes (address translation G06F12/00)} · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F13/1642

  with request queuing · CPC title

• G06F2212/6046

  Using a specific cache allocation policy other than replacement policy · CPC title

• G06F9/3824

  Operand accessing · CPC title