Composable transceiver using low bit count inputs and outputs

Patent metadata

Field	Value
Publication number	US-10707913-B2
Application number	US-201816121510-A
Country	US
Kind code	B2
Filing date	Sep 4, 2018
Priority date	Sep 4, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A radio frequency system. In some embodiments, the system includes a one-bit receiver, and the one-bit receiver includes a digital pseudo random noise generator, a one-bit digital to analog converter, a power combiner, a one-bit analog to digital converter, and a digital subtraction circuit. The digital pseudo random noise generator produces a signal added to the received signal before analog to digital conversion. After analog to digital conversion, a delayed version of the dither is subtracted from the digital signal.

First claim

What is claimed is:

1. A radio frequency system, comprising:
a one-bit receiver, having a radio frequency input and a digital output, and comprising:
a digital pseudo random noise generator;
a one-bit digital to analog converter, having an input connected to an output of the digital pseudo random noise generator;
a power combiner, having a first input connected to an output of the one-bit digital to analog converter and a second input connected to the radio frequency input;
a one-bit analog to digital converter, having an input operatively coupled to an output of the power combiner;
a shift register, having an input connected to the digital pseudo random noise generator; and
a digital subtraction circuit, having a first input connected to an output of the one-bit analog to digital converter, a second input operatively coupled to an output of the shift register, and an output connected to the digital output of the one-bit receiver,

wherein:
the digital pseudo random noise generator,
the one-bit digital to analog converter,
the one-bit analog to digital converter,
the shift register, and
the digital subtraction circuit

are implemented in a field programmable gate array, and
wherein:
the one-bit analog to digital converter is a serial receiver.

2. The radio frequency system of claim 1 , further comprising an attenuator connected between the output of the power combiner and the input of the one-bit analog to digital converter.

3. The radio frequency system of claim 1 , wherein:
the one-bit digital to analog converter is a serial transmitter.

4. The radio frequency system of claim 1 , wherein the digital pseudo random noise generator comprises a linear feedback shift register.

5. The radio frequency system of claim 1 , further comprising a digital filter having an input connected to the digital output of the one-bit receiver.

6. The radio frequency system of claim 5 , wherein the digital filter is an infinite impulse response filter.

7. The radio frequency system of claim 6 , wherein the digital filter is an integrator.

8. A radio frequency system, comprising:
a one-bit receiver, having a radio frequency input and a digital output, and comprising:
a digital pseudo random noise generator;
a one-bit digital to analog converter, having an input connected to an output of the digital pseudo random noise generator;
a power combiner, having a first input connected to an output of the one-bit digital to analog converter and a second input connected to the radio frequency input;
a one-bit analog to digital converter, having an input operatively coupled to an output of the power combiner; and
a digital subtraction circuit, having a first input connected to an output of the one-bit analog to digital converter, a second input operatively coupled to the output of the digital pseudo random noise generator, and an output connected to the digital output of the one-bit receiver,

the radio frequency system further comprising:
a one-bit transmitter having a digital input and an analog output, and comprising
a digital pseudo random noise generator,
a first digital adding circuit,
a digital integrator,
a second digital adding circuit,
a digital comparator,
a one-bit digital to analog converter, and
a digital gain circuit,

wherein
the digital pseudo random noise generator of the one-bit transmitter has an output;
the first digital adding circuit has:
a first input, connected to the output of the digital pseudo random noise generator of the one-bit transmitter,
a second input, and
an output,

the digital integrator has:
an input connected to the output of the first digital adding circuit, and
an output;

the second digital adding circuit has:
a first input, connected to the output of the digital integrator,
a second input, connected to the digital input of the one-bit transmitter, and
an output,

the digital comparator has:
a first input, connected to the output of the second digital adding circuit,
a second input, connected to a digital constant, and
an output,

the one-bit digital to analog converter of the one-bit transmitter has:
an input, connected to the output of the digital comparator, and
an output, connected to the analog output of the one-bit transmitter; and

the digital gain circuit has:
an input, connected to the output of the digital comparator,
an output, connected to the second input of the first digital adding circuit, and
a low-frequency gain exceeding one.

9. The radio frequency system of claim 8 , wherein the digital constant is zero.

10. The radio frequency system of claim 8 , wherein:
the digital pseudo random noise generator of the one-bit transmitter,
the first digital adding circuit,
the digital integrator,
the second digital adding circuit,
the digital comparator,
the one-bit digital to analog converter of the one-bit transmitter, and
the digital gain circuit,

are implemented in a field programmable gate array.

11. The radio frequency system of claim 10 , wherein:
the one-bit digital to analog converter of the one-bit transmitter is a serial transmitter.

12. The radio frequency system of claim 8 , wherein the digital pseudo random noise generator of the one-bit transmitter comprises a linear feedback shift register.

13. The radio frequency system of claim 8 , wherein the digital gain circuit is an infinite impulse response filter.

14. The radio frequency system of claim 8 , wherein the digital gain circuit is configured to perform multiplication by a constant.

15. The radio frequency system of claim 8 , wherein the digital gain circuit is a left-shift circuit.

16. The radio frequency system of claim 8 , wherein:
the one-bit digital to analog converter of the one-bit receiver is a serial transmitter.

17. The radio frequency system of claim 8 , wherein:
the one-bit digital to analog converter of the one-bit receiver is a serial transmitter,
the one-bit analog to digital converter of the one-bit receiver is a serial receiver, and
the one-bit digital to analog converter of the one-bit transmitter is a serial transmitter.

18. A radio frequency system, comprising:
a one-bit receiver, having a radio frequency input and a digital output, and comprising:
a digital pseudo random noise generator;
a one-bit digital to analog converter, having an input connected to an output of the digital pseudo random noise generator;
a power combiner, having a first input connected to an output of the one-bit digital to analog converter and a second input connected to the radio frequency input;
a one-bit analog to digital converter, having an input operatively coupled to an output of the power combiner; and
a digital subtraction circuit, having a first input connected to an output of the one-bit analog to digital converter, a second input operatively coupled to the output of the digital pseudo random noise generator, and an output connected to the digital output of the one-bit receiver, wherein:

the first input of the power combiner is connected to the output of the one-bit digital to analog converter through a first switch,
the second input of the power combiner is connected to the radio frequency input of the one-bit receiver through a second switch,
the output of the power combiner is connected to the input of the one-bit analog to digital converter through a third switch and an attenuator, and
the second input of the power combiner is connected to the output of the power combiner through a fourth switch.

Assignees

• Raytheon Co

Inventors

• Marr Harry B
• Thompson Daniel
• Robinson Ian S

Classifications

• H04B1/40 Primary

  Circuits · CPC title

• H04L25/0212

  of impulse response · CPC title

• H03M3/332

  in particular a pseudo-random signal · CPC title

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• H03M7/3042

  the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only · CPC title