Transition state acquisition device, time-to-digital converter, and A/D conversion circuit

Patent metadata

Field	Value
Publication number	US-10707891-B2
Application number	US-201916360077-A
Country	US
Kind code	B2
Filing date	Mar 21, 2019
Priority date	Mar 22, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A transition state acquisition device includes an oscillator that includes a tapped delay line and a combination circuit provided on a signal path from one end to the other end of the tapped delay line, and oscillates based on a first signal, and a latch that captures and holds an output signal of the tapped delay line in synchronization with a second signal. The oscillator starts a transition of a state of the tapped delay line based on the first signal. An interval between timings at which the latch captures the output signals of the tapped delay line is shorter than a time during which the state transition of the tapped delay line makes one round.

First claim

What is claimed is:

1. A transition state acquisition device comprising:
an oscillator that includes a tapped delay line and a combination circuit provided on a signal path from one end to the other end of the tapped delay line, and oscillates based on a first signal; and
a latch that captures and holds an output signal of the tapped delay line in synchronization with a second signal,
wherein the oscillator starts a transition of a state of the tapped delay line based on the first signal, and
wherein an interval between timings at which the latch captures the output signals of the tapped delay line is shorter than a time during which the state transition of the tapped delay line makes one round.

2. The transition state acquisition device according to claim 1 ,
wherein the oscillator includes a plurality of the tapped delay lines and at least some of the plurality of tapped delay lines are connected in parallel, and
wherein in a transition of values of a plurality of specific signals output from the plurality of tapped delay lines, a Hamming distance before and after the transition is 1.

3. The transition state acquisition device according to claim 1 , further comprising:
a counter that counts the number of times the state of the tapped delay line transitions based on a value held by the latch.

4. The transition state acquisition device according to claim 2 , further comprising:
a counter that counts the number of times the state of the tapped delay line transitions based on a value held by the latch,
wherein the counter
obtains a first count value as an approximate value of the number of times the state of the tapped delay line transitions based on values that the latch captures and holds the plurality of specific signals,
obtains a second count value by specifying the tapped delay line of which the state is transitioned at a timing when the latch captures the plurality of specific signals among the plurality of tapped delay lines based on the values that the latch captures and holds the plurality of specific signals and by performing a population count with respect to the value that the latch captures and holds the signal output from the specified tapped delay line, and
obtains the number of times the state of the tapped delay line transitions based on the first count value and the second count value.

5. A time-to-digital converter comprising:
the transition state acquisition device according to claim 3 ;
a count value holder that captures and holds a count value counted by the counter of the transition state acquisition device; and
an integrator that integrates the count value held by the count value holder to generate a first time-to-digital value corresponding to a time interval between a time event of the first signal and a time event of the second signal.

6. The time-to-digital converter according to claim 5 ,
wherein the time event of the second signal is set independently of the time event of the first signal.

7. The time-to-digital converter according to claim 5 , further comprising:
a time-to-digital value generator,
wherein the oscillator starts a transition of a state of the tapped delay line based on each of a plurality of the first signals,
wherein the counter counts the number of times the state of the tapped delay line transitions with respect to each of the plurality of first signals,
wherein the count value holder captures and holds a plurality of the count values counted by the counter,
wherein the integrator integrates each of the plurality of count values held by the count value holder to generate a plurality of the first time-to-digital values corresponding to a time interval between the time event of each of the plurality of first signals and the time event of the second signal, and
wherein the time-to-digital value generator generates a second time-to-digital value corresponding to a time interval of at least two time events of the plurality of first signals based on the plurality of first time-to-digital values.

8. A time-to-digital converter comprising:
a plurality of the transition state acquisition devices according to claim 3 ;
a plurality of count value holders;
a plurality of integrators; and
a time-to-digital value generator,
wherein the plurality of transition state acquisition devices start a transition of a state of the tapped delay line based on each of a plurality of the first signals,
wherein the plurality of count value holders capture and hold a count value counted by the counter of each of the plurality of transition state acquisition devices,
wherein the plurality of integrators integrate each of the plurality of count values held by the plurality of count value holders to generate a plurality of first time-to-digital values corresponding to a time interval between a time event of each of the plurality of first signals and a time event of the second signal, and
wherein the time-to-digital value generator generates a second time-to-digital value corresponding to a time interval of at least two time events of the plurality of first signals based on the plurality of first time-to-digital values generated by the plurality of integrators.

9. The time-to-digital converter according to claim 8 ,
wherein the time event of the second signal is set independently of the time events of the plurality of first signals.

10. An A/D conversion circuit that converts an input analog signal into a digital signal and outputs the converted digital signal, the circuit comprising:
the time-to-digital converter according to claim 5 ;
a reference waveform signal generation circuit that generates a reference waveform signal based on the second signal; and
a comparator that compares a voltage of the analog signal with a voltage of the reference waveform signal to output the first signal,
wherein the A/D conversion circuit outputs the digital signal based on the first time-to-digital value generated by the time-to-digital converter.

11. An A/D conversion circuit that converts an input analog signal into a digital signal and outputs the converted digital signal, the circuit comprising:
the time-to-digital converter according to claim 5 ;
a sample-hold circuit that samples and holds a voltage of the analog signal;
a reference waveform signal generation circuit that generates a reference waveform signal based on the second signal; and
a comparator that compares a voltage held by the sample-hold circuit with a voltage of the reference waveform signal to output the first signal,
wherein the A/D conversion circuit outputs the digital signal based on the first time-to-digital value generated by the time-to-digital converter.

Assignees

• Seiko Epson Corp

Inventors

• Todorokihara Masayoshi

Classifications

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/502 Primary

  using tapped delay lines · CPC title

• H03M1/1019

  by storing a corrected or correction value in a digital look-up table · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03M1/54

  Input signal sampled and held with linear return to datum · CPC title