Method and apparatus for analog/digital conversion

Patent metadata

Field	Value
Publication number	US-10707888-B2
Application number	US-201916386669-A
Country	US
Kind code	B2
Filing date	Apr 17, 2019
Priority date	Apr 19, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.

First claim

What is claimed is:

1. A method for determining a suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter, wherein the asynchronous successive approximation analog/digital converter comprises a digital/analog converter, the method comprising:
providing the test delay value;
converting a predetermined digital test value into an analog test signal using the digital/analog converter;
approximating the analog test signal in a bit-by-bit manner using the asynchronous successive approximation analog/digital converter, and generating a digital test result based on the approximating; and
determining whether the test delay value is a suitable delay value for operating the asynchronous successive approximation analog/digital converter, determining comprising comparing the digital test result with the predetermined digital test value.

2. The method as claimed in claim 1 , wherein the comparing the digital test result takes into account redundancy areas of the asynchronous successive approximation analog/digital converter.

3. A method for determining an optimized delay value of a comparator circuit of an asynchronous successive approximation analog/digital converter comprising a digital/analog converter and the comparator circuit, the method comprising:
determining a suitability of at least two test delay values between comparator decisions of the comparator circuit of the asynchronous successive approximation analog/digital converter, wherein for each of the at least two test delay values, determining the suitability comprises performing the following steps to produce at least two corresponding digital test results:
providing a respective test delay value of the at least two test delay values;
converting a predetermined digital test value into an analog test signal using the digital/analog converter,
approximating the analog test signal in a bit-by-bit manner using the asynchronous successive approximation analog/digital converter, and generating a corresponding digital test result of the at least two corresponding digital test results based on the approximating,
determining whether the respective test delay value is a suitable delay value for operating the asynchronous successive approximation analog/digital converter, determining comprising comparing the corresponding digital test result with the predetermined digital test value; and

determining the optimized delay value comprising comparing the at least two corresponding digital test results.

4. The method as claimed in claim 3 , wherein:
the at least two test delay values are generated successively and in a monotonously increasing manner;
the method further comprises determining that a termination condition is satisfied when the respective test delay value is determined to be the suitable delay value; and
the respective test delay value that resulted in the termination condition being achieved is determined to be the optimized delay value.

5. The method as claimed in claim 3 , wherein the at least two test delay values are generated using an interval interleaving method.

6. The method as claimed in claim 5 , wherein the interval interleaving method comprises a binary search.

7. The method as claimed in claim 3 , wherein optimized delay values are determined for at least two different bits and a global delay value is determined as the maximum of the at least two different optimized delay values.

8. The method as claimed in claim 3 , wherein optimized delay values are determined for at least three different bits and at least two selected delay values are selected from three optimized delay values, wherein one of at least two selected delay values is assigned to each bit produced by the successive approximation analog/digital converter.

9. The method as claimed in claim 8 , wherein an optimized delay value is determined for each bit produced by the successive approximation analog/digital converter.

10. An apparatus for successive approximation analog/digital conversion, the apparatus comprising:
a digital/analog converter;
an asynchronous approximation register;
a delay circuit; and
a time calibration circuit, wherein the time calibration circuit is configured to:
provide a test delay value,
convert a predetermined digital test value into an analog test signal using the digital/analog converter,
approximate the analog test signal in a bit-by-bit manner using digital/analog converter and the asynchronous approximation register, and generating a digital test result based on the approximating, and
determine whether the test delay value is a suitable delay value for performing the successive approximation analog/digital conversion, determining comprising comparing the digital test result with the predetermined digital test value.

11. An apparatus for analog/digital conversion, the apparatus comprising:
an asynchronous successive approximation analog/digital converter comprising:
a digital/analog converter,
an approximation register,
a comparator circuit,
an adjustable delay circuit configured to stipulate a delay between decisions of the comparator circuit, and
a time calibration circuit;

wherein the asynchronous successive approximation analog/digital converter is configured to:
receive a predetermined digital test value and to convert the predetermined digital test value into an analog test signal using the digital/analog converter, and
approximate the analog test signal in a bit-by-bit manner on based on a multiplicity of comparator decisions to provide a digital test result; and

wherein the time calibration circuit is configured to compare the digital test result with the predetermined digital test value and to determine a suitability of at least one test delay value based on comparing the predetermined digital test value with the digital test result.

12. The apparatus as claimed in claim 11 , wherein the time calibration circuit configured to:
provide the asynchronous successive approximation analog/digital converter with the predetermined digital test value and the at least one test delay value; and
set the delay of the delay circuit.

13. The apparatus as claimed in claim 11 , wherein the digital/analog converter comprises a capacitive arrangement, and the received predetermined digital test value is converted into the analog test signal by setting the capacitive arrangement in a redistribution phase or in a sampling phase of the analog/digital converter according to the digital test value.

14. The apparatus as claimed in claim 11 , wherein the time calibration circuit is further configured to determine an optimized delay value based on comparing a plurality of comparator results for at least two different test delay values.

15. The apparatus as claimed in claim 14 , wherein the at least two different test delay values are generated using an interval interleaving method.

16. The apparatus as claimed in claim 15 , wherein the interval interleaving method comprises a binary search.

17. The apparatus as claimed in claim 11 , wherein the delay circuit has at least two different delay values and is set up to provide these values in response to a decision by the comparator circuit.

18. The apparatus as claimed in claim 11 , wherein the apparatus is configured to determine an optimized delay value by comparing two digital test results.

19. The apparatus as claimed in claim 17 , wherein an optimized delay value is determined for each bit produced by the succes

Assignees

• Infineon Technologies Ag

Inventors

• Pernull Martin
• Bogner Peter

Classifications

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/125

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title