Ring voltage-controlled oscillator and phase-locked loop

Patent metadata

Field	Value
Publication number	US-10707844-B2
Application number	US-201716312345-A
Country	US
Kind code	B2
Filing date	Jun 21, 2017
Priority date	Jun 30, 2016
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.

First claim

What is claimed is:

1. A ring voltage control oscillator, comprising:
a conversion unit configured to receive an externally controlled voltage signal, and output a control current signal;
cascaded multistage delay units configured to receive the control current signal outputted by the conversion unit; wherein the delay unit comprises two signal input terminals and two signal output terminals;
a first signal output terminal and a second signal output terminal of the delay unit are correspondingly connected to a first signal input terminal and a second signal input terminal of a next stage of the delay unit, respectively;
a first signal output terminal and a second signal output terminal of a last stage of the delay unit are correspondingly connected to a second signal input terminal and a first signal input terminal of a first stage of the delay unit, respectively;
multistage isolation buffer units configured to receive the control current signal outputted by the conversion unit; wherein the isolation buffer unit comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit are connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit, respectively;
wherein clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffer units have a first phase difference;
wherein second signal output terminals of two adjacent stages of the isolation buffer units correspondingly output clock signals having a second phase difference equal to the first phase difference;
wherein the delay unit comprises a first inverting circuit, a second inverting circuit, a first MOS transistor, a second MOS transistor, and a trans-coupling circuit;
an input terminal and an output terminal of the first inverting circuit correspondingly serve as the first signal input terminal and the second signal output terminal of the delay unit, respectively;
an input terminal and an output terminal of the second inverting circuit correspondingly serve as the second signal input terminal and the first signal output terminal of the delay unit, respectively;
both a gate and a drain of the first MOS transistor are connected to the output terminal of the first inverting circuit;
a first control terminal of the trans-coupling circuit is connected to the output terminal of the second inverting circuit;
a second control terminal of the trans-coupling circuit is connected to the output terminal of the first inverting circuit;
both a gate and a drain of the second MOS transistor are connected to the output terminal of the second inverting circuit;
both a source of the first MOS transistor and a source of the second MOS transistor are grounded, wherein the first MOS transistor and the second MOS transistor are both first conductivity type MOS transistors; and
both a power supply terminal of the first inverting circuit and a power supply terminal of the second inverting circuit are connected to the power source.

2. The ring voltage control oscillator of claim 1 , wherein a first signal outputted by the first signal output terminal of the delay unit is inverted relative to a second signal outputted by the second signal output terminal of the delay unit.

3. The ring voltage control oscillator of claim 1 , wherein the first inverting circuit comprises a third MOS transistor and a fourth MOS transistor;
a gate of the third MOS transistor is connected to a gate of the fourth MOS transistor; the gate of the third MOS transistor serves as the input terminal of the first inverting circuit; a drain of the third MOS transistor is connected to a drain of the fourth MOS transistor; the drain of the third MOS transistor serves as the output terminal of the first inverting circuit; a source of the third MOS transistor is connected to the power source; and a source of the fourth MOS transistor is grounded;
the fourth MOS transistor is a first conductivity type MOS transistor; and the third MOS transistor is a second type conductivity MOS transistor.

4. The ring voltage control oscillator of claim 3 , wherein the second inverting circuit comprises a fifth MOS transistor and a sixth MOS transistor;
a gate of the fifth MOS transistor is connected to a gate of the sixth MOS transistor; the gate of the fifth MOS transistor serves as the input terminal of the second inverting circuit; a drain of the fifth MOS transistor is connected to a drain of the sixth MOS transistor; the drain of the fifth MOS transistor serves as the output terminal of the second inverting circuit; a source of the fifth MOS transistor is connected to the power source; and a source of the sixth MOS transistor is grounded;
the sixth MOS transistor is a first conductivity type MOS transistor; and the fifth MOS transistor is a second type conductivity MOS transistor.

5. The ring voltage control oscillator of claim 4 , wherein the delay unit further comprises a ninth MOS transistor and a tenth MOS transistor;
a source of the ninth MOS transistor is connected to the power source; a gate of the ninth MOS transistor is connected to the conversion unit; and a drain of the ninth MOS transistor is connected to a source of the tenth MOS transistor;
a gate of the tenth MOS transistor is connected to the conversion unit; and a drain of the tenth MOS transistor is connected to the drain of the third MOS transistor and the drain of the fifth MOS transistor;
wherein, both the ninth MOS transistor and the tenth MOS transistor are the second conductivity type MOS transistors.

6. The ring voltage control oscillator of claim 4 , wherein the first MOS transistor and the second MOS transistor, the third MOS transistor and the fifth MOS transistor, the fourth MOS transistor and the sixth MOS transistor are centrally symmetrically arranged, respectively.

7. The ring voltage control oscillator of claim 4 , wherein the first conductivity type MOS transistor is an N type MOS transistor; and the second conductivity type MOS transistor is a P type MOS transistor.

8. The ring voltage control oscillator of claim 3 , wherein the trans-coupling circuit comprises a seventh MOS transistor and an eighth MOS transistor;
a drain of the seventh MOS transistor is connected to the output terminal of the first inverting circuit; a gate of the seventh MOS transistor is connected to the output terminal of the second inverting circuit;
a drain of the eighth MOS transistor is connected to the output terminal of the second inverting circuit; a gate of the eighth MOS transistor is connected to the output terminal of the first inverting circuit;
sources of the seventh MOS transistor and the eighth MOS transistor are grounded;
wherein both the seventh MOS transistor and the eighth MOS transistor are first type MOS transistors.

9. The ring voltage control oscillator of claim 1 , wherein the isolation buffer unit is a fully differential structure circuit comprising a first amplification circuit, a second amplification circuit, a first digital inverter and a second digital inverter;
an input terminal of the first amplification circuit is the first signal input terminal of the isolation buffer unit and is connected to the first signal output terminal of the delay unit; an input terminal of the second amplification circuit is the second signal input terminal of the isolation buffer unit and is connected to the second signal output terminal of the delay unit;
both power supply terminals of the first amplification circuit and the second amplification circuit are connected to the power source;
an output terminal of the first amplification circuit is connected to an input termi

Assignees

• Csmc Technologies Fab2 Co Ltd

Inventors

• Wang Xueyan
• Chen Qiang

Classifications

• H03K5/134 Primary

  with field-effect transistors · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03K3/0322

  with differential cells · CPC title

• H03K3/03

  Astable circuits · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title