Power regulation with charge pumps

Patent metadata

Field	Value
Publication number	US-10707753-B2
Application number	US-201715708379-A
Country	US
Kind code	B2
Filing date	Sep 19, 2017
Priority date	Sep 19, 2017
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

The present disclosure describes aspects of power regulation with charge pumps. In some aspects, an integrated circuit (IC) includes multiple processor cores and a power input connected to an internal power rail of the IC. The IC may also comprise embedded charge pumps coupled between the internal power rail of the IC and respective input power rails of the multiple processor cores. Capacitors of the embedded charge pumps may be implemented with on-die capacitors suitable for integration with a die of the circuit to facilitate the embedding of the charge pumps. Alternately or additionally, separate input power rails of the processor cores and the embedded charge pumps may enable more-efficient power regulation or power management on a per-processor core basis, such as when a processor core is throttled or idled to reduce power consumption.

First claim

What is claimed is:

1. An integrated circuit comprising:
a power input connected to an internal power rail of the integrated circuit;
multiple processor cores that include a first processor core and a second processor core;
multiple charge pumps that include:
a first charge pump coupled between the internal power rail of the integrated circuit and a first input power rail of the first processor core; and
a second charge pump coupled between the internal power rail of the integrated circuit and a second input power rail of the second processor core, the second input power rail of the second processor core isolated from the first input power rail of the first processor core; and

a signal line coupled from the internal power rail of the integrated circuit to an external contact of the integrated circuit.

2. The integrated circuit as recited in claim 1 , wherein:
the integrated circuit is disposed on an integrated circuit die; and
at least one of the first charge pump or the second charge pump is implemented with capacitors that are embodied on the integrated circuit die.

3. The integrated circuit as recited in claim 2 , wherein the capacitors of the first charge pump or the second charge pump are implemented as at least one of:
metal-insulator-metal capacitors;
metal-on-metal capacitors; or
metal-oxide-metal capacitors.

4. The integrated circuit as recited in claim 2 , wherein a capacitance value of one or more of the capacitors is within a range of approximately five nanofarads to 50 nanofarads.

5. The integrated circuit as recited in claim 1 , wherein the first charge pump or the second charge pump comprises one of:
a divide-by-two charge pump;
a divide-by-three charge pump; or
a divide-by-four charge pump.

6. The integrated circuit as recited in claim 1 , wherein the integrated circuit is implemented without:
a power control switch disposed between the first charge pump and the first input power rail of the first processor core; or
a power control switch disposed between the second charge pump and the second input power rail of the second processor core.

7. The integrated circuit as recited in claim 1 , further comprising a charge pump controller that includes:
an input coupled to the first input power rail of the first processor core or the second input power rail of the second processor core; and
an output coupled to first switch devices of the first charge pump or second switch devices of the second charge pump.

8. The integrated circuit as recited in claim 1 , wherein switch devices of the first charge pump or the second charge pump are connected to a clock source of the integrated circuit that is configured to operate at a frequency of at least 200 megahertz.

9. The integrated circuit as recited in claim 1 , wherein:
the first processor core or the second processor core is implemented with low-voltage switching devices that are configured to operate from approximately 0.5 volts to 1.5 volts; and
the first charge pump or the second charge pump is implemented with other low-voltage switching devices that are configured operate from approximately 0.5 volts to 1.5 volts.

10. The integrated circuit as recited in claim 1 , wherein the integrated circuit is implemented as a system-on-chip, an application-specific integrated circuit, an application processor, a graphics processor, a memory controller, or a modem.

11. A printed circuit board assembly (PCBA) comprising:
a switching regulator that includes:
a first switch coupled between a power rail of the PCBA and a first terminal of an inductor of the switching regulator;
a second switch coupled between a lower potential of the PCBA and the first terminal of the inductor of the switching regulator; and
a capacitor connected between a second terminal of the inductor and the lower potential of the PCBA; and

an integrated circuit that includes:
an internal power rail coupled, via a power input node, to the second terminal of the inductor of the switching regulator;
multiple processor cores that include a first processor core and a second processor core; and
multiple charge pumps that include:
a first charge pump coupled between the internal power rail of the integrated circuit and a first input power rail of the first processor core; and
a second charge pump coupled between the internal power rail of the integrated circuit and a second input power rail of the second processor core, the second input power rail of the second processor core not coupled to the first input power rail of the first processor core,
wherein a first frequency or first duty cycle at which the first charge pump is configured to operate is different from a second frequency or second duty cycle at which the second charge pump is configured to operate.

12. The printed circuit board assembly as recited in claim 11 , wherein:
the first charge pump is connected directly from the internal power rail of the integrated circuit to the first input power rail of the first processor core; and
the second charge pump is connected directly from the internal power rail of the integrated circuit to the second input power rail of the second processor core.

13. The printed circuit board assembly as recited in claim 11 , wherein:
the integrated circuit is disposed on an integrated circuit die; and
the first charge pump or the second charge pump is implemented with capacitors that are embodied on the integrated circuit die.

14. The printed circuit board assembly as recited in claim 13 , wherein a capacitance value of one or more of the capacitors is within a range of approximately five nanofarads to 50 nanofarads.

15. The printed circuit board assembly as recited in claim 13 , wherein the capacitors of the first charge pump or the capacitors of the second charge pump are implemented as metal-insulator-metal capacitors, metal-on-metal capacitors, or metal-oxide-metal capacitors.

16. The printed circuit board assembly as recited in claim 11 , wherein a first voltage of the first input power rail of the first processor core is different from a second voltage of the second input power rail of the second processor core.

17. The printed circuit board assembly as recited in claim 11 , wherein:
the first processor core comprises a first digital load of the integrated circuit;
the second processor core comprises a second digital load of the integrated circuit; and
the integrated circuit further comprises:
a third digital load; and
a third charge pump coupled between the internal power rail of the integrated circuit and an input power rail of the third digital load of the integrated circuit.

18. The printed circuit board assembly as recited in claim 17 , wherein the third digital load of the integrated circuit comprises one of a third processor core, a graphics processing unit, a digital signal processor, a baseband modem, a communications processor, a memory controller, or a memory module.

19. The printed circuit board assembly as recited in claim 11 , wherein the printed circuit board assembly is embodied in one of a smart-phone, set-top box, cellular base station, access point, cellular phone, gaming device, navigation device, laptop computer, tablet computer, smart appliance, or vehicle-based communication system.

20. The printed circuit board assembly as recited in claim 11 , wherein the first input power rail is coupled to an external contact of the integrated circuit.

21. The printed circuit board assembly as recited in claim 20 , wherein

Assignees

• Qualcomm Inc

Inventors

• Koski Marko
• Tuten Charles

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M7/003

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• G06F1/266

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title