TFT substrate, scanning antenna provided with TFT substrate, and method for producing TFT substrate

Patent metadata

Field	Value
Publication number	US-10707350-B2
Application number	US-201716345284-A
Country	US
Kind code	B2
Filing date	Oct 31, 2017
Priority date	Nov 9, 2016
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A source terminal section of a TFT substrate includes a source terminal lower connection section included in a gate metal layer, and a source terminal upper connection section included in a conductive layer. A source gate connection section includes a source lower connection wiring line included in the gate metal layer and connected to the source terminal lower connection section, a source bus connection section included in a source metal layer and connected to a source bus line, and a source upper connection section included in a conductive layer, and the source upper connection section is in contact with the source lower connection wiring line within a third opening formed in a gate insulating layer and in contact with the source bus connection section within a fifth opening formed in an interlayer insulating layer.

First claim

The invention claimed is:

1. A TFT substrate including a dielectric substrate and a plurality of antenna unit regions arranged on the dielectric substrate, each of the plurality of antenna unit regions including a TFT and a patch electrode connected to a drain electrode of the TFT, and the TFT substrate further including a transmission and/or reception region including the plurality of antenna unit regions and a non-transmission and/or reception region located on a region other than the transmission and/or reception region, the TFT substrate comprising:
a gate metal layer supported by the dielectric substrate, and including a gate electrode of the TFT and a gate bus line connected to the gate electrode;
a gate insulating layer formed on the gate metal layer;
a source metal layer formed on the gate insulating layer, and including a source electrode of the TFT, the drain electrode, a source bus line connected to the source electrode, and the patch electrode;
an interlayer insulating layer formed on the source metal layer,
a conductive layer formed on the interlayer insulating layer; and
a source terminal section and a source gate connection section disposed in the non-transmission and/or reception region,
wherein the source terminal section includes
a source terminal lower connection section included in the gate metal layer,
a first opening formed in the gate insulating layer and at least reaching the source terminal lower connection section,
a second opening formed in the interlayer insulating layer and overlapping the first opening when viewed from a normal direction of the dielectric substrate, and
a source terminal upper connection section formed on the interlayer insulating layer and included in the conductive layer,
the source terminal upper connection section is in contact with the source terminal lower connection section within the first opening,
the source gate connection section includes
a source lower connection wiring line included in the gate metal layer and connected to the source terminal lower connection section,
a third opening formed in the gate insulating layer and at least reaching the source lower connection wiring line,
a source bus connection section included in the source metal layer and connected to the source bus line,
a fourth opening formed in the interlayer insulating layer and overlapping the third opening when viewed from the normal direction of the dielectric substrate,
a fifth opening formed in the interlayer insulating layer and at least reaching the source bus connection section, and
a source upper connection section formed on the interlayer insulating layer and included in the conductive layer, and
the source upper connection section is in contact with the source lower connection wiring line within the third opening, and in contact with the source bus connection section within the fifth opening.

2. The TFT substrate according to claim 1 ,
wherein the conductive layer includes a transparent conductive layer.

3. The TFT substrate according to claim 1 or 2 ,
wherein the conductive layer includes
a first conductive layer including a transparent conductive layer, and
a second conductive layer formed under the first conductive layer, and formed of at least one layer selected from a group including a Ti layer, a MoNb layer, a MoNbNi layer, a MoW layer, a W layer, and a Ta layer.

4. The TFT substrate according to claim 1 ,
wherein a side surface of the first opening and a side surface of the second opening are aligned.

5. The TFT substrate according to claim 1 ,
wherein a side surface of the third opening and a side surface of the fourth opening are aligned.

6. The TFT substrate according to claim 1 , further comprising:
a gate terminal section disposed in the non-transmission and/or reception region,
wherein the gate terminal section includes
a gate terminal lower connection section included in the gate metal layer and connected to the gate bus line,
a sixth opening formed in the gate insulating layer and at least reaching the gate terminal lower connection section,
a seventh opening formed in the interlayer insulating layer and overlapping the sixth opening when viewed from the normal direction of the dielectric substrate, and
a gate terminal upper connection section formed on the interlayer insulating layer and included in the conductive layer, and
the gate terminal upper connection section is in contact with the gate terminal lower connection section within the sixth opening.

7. The TFT substrate according to claim 1 , further comprising:
a transfer terminal section disposed in the non-transmission and/or reception region,
wherein the transfer terminal section includes
a transfer terminal lower connection section included in the gate metal layer,
an eighth opening formed in the gate insulating layer and at least reaching the transfer terminal lower connection section,
a ninth opening formed in the interlayer insulating layer and overlapping the eighth opening when viewed from the normal direction of the dielectric substrate, and
a transfer terminal upper connection section formed on the interlayer insulating layer and included in the conductive layer, and
the transfer terminal upper connection section is in contact with the transfer terminal lower connection section within the eighth opening.

8. The TFT substrate according to claim 7 ,
wherein the eighth opening is inside the transfer terminal lower connection section when viewed from the normal direction of the dielectric substrate.

9. The TFT substrate according to claim 7 ,
wherein the transfer terminal upper connection section includes a portion not overlapping the transfer terminal lower connection section within the eighth opening when viewed from the normal direction of the dielectric substrate.

10. The TFT substrate according to claim 7 ,
wherein a portion in the transfer terminal lower connection section within the eighth opening is covered by the transfer terminal upper connection section.

11. The TFT substrate according to claim 1 ,
wherein a further conductive layer is not included between the source metal layer and the conductive layer, or on the conductive layer.

12. The TFT substrate according to claim 1 ,
wherein each of the terminal sections disposed in the non-transmission and/or reception region does not include a conductive portion included in the source metal layer.

13. A scanning antenna comprising:
the TFT substrate according to claim 1 ;
a slot substrate disposed to face the TFT substrate;
a liquid crystal layer provided between the TFT substrate and the slot substrate; and
a reflective conductive plate disposed to face a surface of the slot substrate on a side opposite to the liquid crystal layer with a dielectric layer interposed between the reflective conductive plate and the surface,
wherein the slot substrate includes another dielectric substrate and a slot electrode formed on a surface of the other dielectric substrate on a side of the liquid crystal layer, and
the slot electrode includes a plurality of slots, the plurality of slots being arranged corresponding to the patch electrodes of the plurality of antenna unit regions of the TFT substrate.

14. A manufacturing method of the TFT substrate that is according to claim 1 , the manufacturing method comprising:
(a) forming the gate metal layer on the dielectric substrate;
(b) depositing a first insulating film on the gate metal layer;
(c) forming the source metal layer on the first insulating film;
(d) depositing a second insulating film on the source metal layer;
(e) forming the secon

Assignees

• Sharp Kk

Inventors

• Misaki Katsunori

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6758 Primary

  characterised by the insulating substrates · CPC title

• Y02P80/30

  Reducing waste in manufacturing processes; Calculations of released waste quantities · CPC title