Resistive memory cell having a compact structure

Patent metadata

Field	Value
Publication number	US-10707270-B2
Application number	US-201916357152-A
Country	US
Kind code	B2
Filing date	Mar 18, 2019
Priority date	Jun 23, 2015
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

First claim

The invention claimed is:

1. A process for fabricating an integrated circuit having a first memory cell, the process comprising:
forming a selection transistor of the first memory cell on a semiconductor substrate covered with a first insulating layer, the first insulating layer being covered with a semiconductive active layer, the selection transistor including a control gate and first and second conduction terminals;
covering with a second insulating layer a lateral flank of the control gate on a same side as the first conduction terminal;
producing a first trench through the active layer in the first conduction terminal, reaching the first insulating layer;
depositing a layer of a variable-resistance material in the first trench, covering a lateral flank of the active layer in the first trench; and
forming, in the layer of variable-resistance material, a trench conductor reaching the first insulating layer.

2. The process according to claim 1 , wherein forming the trench conductor includes applying an anisotropic etch to the layer of variable-resistance material, until the first insulating layer at the bottom of the first trench is reached, and filling the first trench with a conductor.

3. The process according to claim 1 , wherein forming the trench conductor includes etching a second trench into the layer of variable-resistance material through a mask, and filling the second trench with a conductor.

4. The process according to claim 1 , wherein forming the trench conductor includes separating the layer of variable-resistance material at the bottom of the first trench into first and second portions respectively forming first and second variable-resistance elements of the first memory cell and a second memory cell sharing the trench conductor.

5. The process according to claim 1 , wherein the lateral flank of the layer of variable-resistance material includes a lower flank and an upper flank, the lower flank contacting the trench conductor, process further comprising forming a trench isolation positioned between the trench conductor and the upper flank.

6. The process according to claim 5 , wherein the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

7. The process according to claim 1 , wherein covering with the second insulating layer includes forming a portion of the second insulating layer on a portion of a top of the control gate and depositing the layer of a variable-resistance material includes covering the portion of the top of the control gate with a portion of the layer of variable-resistance material.

8. A process, comprising:
forming a first insulating layer on a semiconductor substrate;
forming a semiconductor layer on the first insulating layer;
forming a selection transistor including a control gate on the semiconductor layer and first and second conduction terminals in the semiconductor layer;
encapsulating the control gate with a second insulating layer;
forming a first trench by removing a portion of the semiconductor layer at the first conduction terminal, the first trench extending to the first insulating layer;
forming a layer of a variable-resistance material on a lateral flank of the control gate and a lateral flank of the semiconductor layer in the first trench and on a top side of the control gate; and
forming a trench conductor in the first trench coupled to the variable-resistance material and extending to the first insulating layer.

9. The process of claim 8 , wherein forming the trench conductor includes applying an anisotropic etch to the layer of variable-resistance material until exposing a portion of the first insulating layer in the first trench, and filling the first trench with a conductive material.

10. The process of claim 8 , wherein forming the selection transistor includes:
implanting a doped region in the semiconductor layer; and
forming the first trench through the doped region, thereby isolating a first portion of the doped region from a second portion of the doped region, the first portion of the doped region being the first conduction terminal of the selection transistor of a first memory cell and the second portion of the doped region being a conduction terminal of a second memory cell.

11. The process of claim 10 , wherein forming the trench conductor includes isolating a first portion of the variable-resistance material from a second portion of the variable-resistance material, the first portion of the variable-resistance material being a variable-resistance element of the first memory cell and the second portion of the variable-resistance material being a variable-resistance element of the second memory cell.

12. The process of claim 8 , further comprising:
coupling a source line to the second conduction terminal;
coupling a bit line to the first conduction terminal; and
coupling a word line to the control gate.

13. The process according to claim 8 , wherein the lateral flank of the layer of variable-resistance material includes a lower flank and an upper flank, the lower flank contacting the trench conductor, process further comprising forming a trench isolation positioned between the trench conductor and the upper flank.

14. The process according to claim 13 , wherein the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

15. A process for fabricating an integrated circuit having a first memory cell, the process comprising:
forming a selection transistor of the first memory cell, the selection transistor including a control gate formed on a semiconductor body and first and second conduction terminals formed in the semiconductor body;
forming an insulating layer on a lateral flank of the control gate and on the first conduction terminal;
producing a first trench in the semiconductor body;
depositing a layer of variable-resistance material in the first trench, covering a lateral flank of the first conduction terminal, wherein the lateral flank of the layer of variable-resistance material includes a lower flank and an upper flank;
forming a trench isolation on the layer of variable-resistance material; and
forming a trench conductor in the in the layer of variable-resistance material, wherein the trench isolation is positioned between the trench conductor and the upper flank.

16. The process according to claim 15 , wherein the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

17. The process according to claim 15 , wherein forming the insulating layer includes forming a portion of the insulating layer on a portion of a top of the control gate and depositing the layer of a variable-resistance material includes covering the portion of the top of the control gate with a portion of the layer of variable-resistance material.

18. The process according to claim 15 , wherein forming the trench conductor by performing an anisotropic etch through the layer of variable-resistance material and by filling the first trench with a conductor.

19. The process according to claim 15 , wherein forming the trench conductor includes etching a second trench into the layer of variable-resistance material through a mask, and filling the second trench with a conductor.

20. The process according to claim 15 , wherein forming the trench conductor includes separating the layer of variable-resistance material at the bottom of the first trenc

Assignees

• St Microelectronics Crolles 2 Sas
• St Microelectronics Rousset

Inventors

• Boivin Philippe
• Jeannot Simon

Classifications

• H10N70/823

  adapted for essentially horizontal current flow, e.g. bridge type devices · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10N70/8836

  Complex metal oxides, e.g. perovskites, spinels · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10N70/245

  the species being metal cations, e.g. programmable metallization cells · CPC title