Method of forming isolation layer

Patent metadata

Field	Value
Publication number	US-10707114-B2
Application number	US-201816049520-A
Country	US
Kind code	B2
Filing date	Jul 30, 2018
Priority date	Jun 13, 2014
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

First claim

What is claimed is:

1. A method of forming an isolation structure, comprising:
providing a shallow trench isolation in a substrate;
providing a vertical structure that includes a source region, a channel region over the source region and a drain region over the channel region, the channel region and the drain region protruding from an isolation layer, the isolation layer including an etch stop layer formed on the source region and the shallow trench isolation and a first ILD layer;
forming a gate dielectric layer over the channel region and the drain region and on the etch stop layer and the first ILD layer;
forming one or more conductive layers over the gate dielectric layer;
providing a second ILD layer over the one or more conductive layers;
performing CMP on the second ILD layer, and stopping the CMP upon reaching an uppermost layer of the one or more conductive layers; and
etching back the second ILD layer to a level corresponding to the channel region.

2. The method of claim 1 , wherein the etching back uses wet etching or plasma etching.

3. The method of claim 1 , wherein the etching back uses gas cluster ion beams.

4. The method of claim 1 , wherein the isolation layer is formed by:
forming a layer for the etch stop layer over the vertical structure, the layer including:
a horizontal upper portion overlying a top of the vertical structure,
a horizontal bottom portion overlying the shallow trench isolation, and
a vertical side portion extending downward from the upper portion and in overlying contact with a side of the source, channel and drain regions;

providing a dielectric layer for the first ILD layer over the etch stop layer's upper, bottom and side portions;
performing CMP on the dielectric layer, and stopping the CMP upon reaching a top of the etch stop layer's upper portion; and
etching back the dielectric layer and the etch stop layer's side portion, thereby exposing the side of the channel and the drain and forming the isolation layer.

5. The method of claim 4 , wherein during the etching back the dielectric layer, the dielectric layer and the etch stop layer's side portion are etched together.

6. The method of claim 4 , wherein the etch stop layer is made of SiN.

7. The method of claim 4 , wherein the vertical structure includes a silicide layer over the drain region formed before the etch stop layer is formed.

8. The method of claim 7 , wherein:
the silicide layer has a top surface and a side, and
the etch stop layer is provided such that the vertical side portion is in overlying contact with the side of the silicide layer.

9. The method of claim 4 , wherein the etching back of the dielectric layer leaves a top surface of the dielectric layer aligned with a top surface of the source region.

10. The method of claim 7 , wherein the etching back the dielectric layer and the etch stop layer removes (i) the etch stop layer's horizontal upper portion and (ii) sections of the etch stop layer's vertical side portions that overlie the channel region, the drain region and the silicide layer, and does not remove sections of the etch stop layer's vertical portions that overlie the source.

11. The method of claim 1 , wherein the gate dielectric layer includes a high-k dielectric layer.

12. The method of claim 1 , wherein the uppermost layer of the one or more conductive layer is a metal gate layer.

13. The method of claim 1 , wherein:
each of the gate dielectric layer and the one or more conductive layer includes a lower horizontal portion that projects horizontally away from a bottom end of the respective vertical portion, and
the method further comprises etching away a distal section of each of the lower horizontal portions, thereby shortening each of the lower horizontal portions.

14. A method of forming an isolation structure, comprising:
providing a vertical structure that includes a source region, a channel region over the source region and a drain region over the channel region, the channel region and the drain region protruding from an isolation layer;
forming a gate dielectric layer over the channel region and the drain region;
forming one or more conductive layers over the gate dielectric layer;
forming a first ILD layer over the one or more conductive layers, the first ILD layer including a top layer, a middle layer and a bottom layer;
performing first CMP on the first ILD layer, and stopping the first CMP so that part of the middle layer remains;
performing second CMP to remove the part of the middle layer and the bottom layer, and stopping the second CMP upon reaching an uppermost layer of the one or more conductive layers; and
etching back the bottom layer to a level corresponding to the channel region,
wherein the top layer is fully removed in the first CMP and the middle layer is fully removed in the second CMP.

15. The method of claim 14 , wherein:
after the CMP is performed, a part of the middle layer remains, and the etching back is performed on the first ILD layer in which the part of the middle layer remains.

16. The method of claim 14 , wherein, before the first ILD layer is formed, part of the gate dielectric layer and the one or more conductive layers is removed by a patterning operation.

17. The method of claim 14 , wherein the middle layer includes at least one selected from the group consisting of SiN, SiON, SiC, SiCN, SiCO and SiCON.

18. The method of claim 14 , wherein a thickness of the middle layer is in a range from 0.5 nm to 30 nm and a thickness of the top layer is in a range from 10 nm to 300 nm.

19. The method of claim 14 , wherein the isolation layer is formed by:
forming an etch stop layer over the vertical structure, the etch stop layer including:
a horizontal upper portion overlying a top of the vertical structure,
a horizontal bottom portion overlying a shallow trench isolation, and
a vertical side portion extending downward from the upper portion and in overlying contact with a side of the source, channel and drain regions;

providing a second ILD layer over the etch stop layer's upper and side portions;
performing third CMP on the second ILD layer, and stopping the third CMP upon reaching a top of the etch stop layer's upper portion; and
etching back the second ILD layer and the etch stop layer's side portion, thereby exposing the side of the channel and the drain and forming the isolation layer.

20. A method of forming an isolation structure, comprising:
providing a shallow trench isolation in a substrate;
providing a vertical structure that includes a source region, a channel region over the source region and a drain region over the channel region, the channel region and the drain region protruding from an isolation layer, the isolation layer including an etch stop layer formed on the source region and the shallow trench isolation and a first ILD layer;
forming a gate dielectric layer over the channel region and the drain region;
forming one or more conductive layers over the gate dielectric layer;
providing a second ILD layer over the one or more conductive layers;
performing CMP on the second ILD layer, and stopping the CMP before reaching an uppermost layer of the one or more conductive layers disposed on an top of the vertical structure, thereby leaving a remaining layer of the second ILD layer to cover a highest portion of a structure disposed over a substrate; and
etching back the second ILD layer with the remaining layer to a level corresponding to the channel region,
wherein a thickness of the rema

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Teng-Chun
• Chen Bing-Hung
• Wang Chien-Hsun
• Lin Cheng-Tung
• Peng Chih-Tang
• Chen De-Fang
• Lin Huan-Just
• Wang Li-Ting
• Lu Yung-Cheng

Classifications

• H10P95/064 Primary

  the removal being chemical etching · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title