Method for polishing a semiconductor wafer

US10707069B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10707069-B2
Application numberUS-201113038455-A
CountryUS
Kind codeB2
Filing dateMar 2, 2011
Priority dateMar 10, 2010
Publication dateJul 7, 2020
Grant dateJul 7, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of polishing a semiconductor wafer includes polishing a surface of the semiconductor wafer using a polishing pad while supplying a polishing agent slurry containing abrasives during a first step. The polishing pad is free of abrasives and includes a first surface that contacts the semiconductor wafer, the first surface having a surface structure including elevations. Supply of polishing agent slurry is subsequently ended and, in a second step, the surface of the semiconductor wafer is polished using the polishing pad while supplying a polishing agent solution having a pH value of at least 12 that is free of solids.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of polishing a semiconductor wafer, the method comprising: polishing a surface of the semiconductor wafer using a polishing pad while supplying a polishing agent slurry containing abrasives during a first step, the polishing pad being free of abrasives and including a first surface that contacts the semiconductor wafer, the first surface having a surface structure including elevations, the structure of the first surface being structured by one of chemical etching, grinding, buffing, sintering or furrowing; subsequently ending the supply of polishing agent slurry; and polishing the surface of the semiconductor wafer so as to decrease a surface roughness of the wafer using the polishing pad in a second step while supplying a polishing agent solution having a pH value of at least 12 that is free of solids. 2. The method as recited in claim 1 , wherein the abrasives in the polishing agent slurry include at least one of the group consisting of oxides of the elements aluminum, cerium, and silicon. 3. The method as recited in claim 1 , wherein the polishing agent slurry is colloidal silica. 4. The method as recited in claim 1 , wherein the polishing pad has a porous matrix. 5. The method as recited in claim 1 , wherein the polishing pad includes at least one of a thermoplastic and a heat-resistant polymer. 6. The method as recited in claim 1 , wherein the surface structure of the first surface of the polishing pad includes at least one of pyramidal structures, tile-shaped structures, round elevations, oval elevations, hexagonal elevations and grooves. 7. The method as recited in claim 1 , further comprising pressing the polishing pad onto the surface of the semiconductor wafer during the first step with a first pressure, and pressing the polishing pad onto the surface of the semiconductor wafer during the second step with a second pressure, the first pressure being greater than the second pressure. 8. The method as recited in claim 1 , wherein the abrasives in the polishing agent slurry includes an oxide of aluminum. 9. The method as recited in claim 1 , wherein the abrasives in the polishing agent slurry includes an oxide of cerium. 10. The method as recited in claim 1 , wherein the abrasives in the polishing agent slurry includes an oxide of silicon. 11. The method as recited in claim 1 , wherein a polishing time in the second step of the polishing with supply of a polishing agent solution is at least 50% of a total polishing time. 12. The method as recited in claim 1 , wherein a polishing time in the second step of the polishing with supply of a polishing agent solution is at least 70% of a total polishing time. 13. The method as recited in claim 1 , wherein a polishing time in the second step of the polishing with supply of a polishing agent solution is at least 85% of a total polishing time. 14. The method as recited in claim 1 , wherein a polishing pressure in the second step of the polishing is in a range of from 70 to 200 hPA. 15. The method as recited in claim 1 , wherein a polishing pressure in the first step of the polishing, when the polishing agent slurry is supplied, is in a range of from 250 to 560 hPA. 16. The method as recited in claim 1 , wherein a polishing pressure in the first step of the polishing, when the polishing agent slurry is supplied, is in a range of from 250 to 400 hPA. 17. The method as recited in claim 1 , wherein a polishing pressure in the first step of the polishing, when the polishing agent slurry is supplied, is in a range of from 250 to 560 hPA. 18. The method as recited in claim 1 , wherein a polishing pressure in the first step of the polishing, when the polishing agent slurry is supplied, is in a range of from 250 to 400 hPA. 19. The method as recited in claim 1 , wherein the pH value of the polishing agent solution in the second step has a pH value of greater than 12. 20. The method as recited in claim 1 , comprising, in the first step: adding abrasives only for starting the polishing, and, immediately after commencing the polishing, removing the abrasives until the polishing it ended, wherein the polishing is effected without addition of abrasive substances and without polishing pads containing abrasives, and wherein the polishing agent slurry initially added serves exclusively as a catalyst that starts the polishing, and is then deactivated.

Assignees

Inventors

Classifications

  • H10P90/129Primary

    by polishing · CPC title

  • H10P52/00Primary

    Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10707069B2 cover?
A method of polishing a semiconductor wafer includes polishing a surface of the semiconductor wafer using a polishing pad while supplying a polishing agent slurry containing abrasives during a first step. The polishing pad is free of abrasives and includes a first surface that contacts the semiconductor wafer, the first surface having a surface structure including elevations. Supply of polishin…
Who is the assignee on this patent?
Schwandner Juergen, Kerstan Michael, Siltronic Ag
What technology area does this patent fall under?
Primary CPC classification H10P90/129. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 07 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).