Nonvolatile memory cell, memory cell unit, and information writing method, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-10706903-B2
Application number	US-201716301063-A
Country	US
Kind code	B2
Filing date	Apr 18, 2017
Priority date	May 31, 2016
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A nonvolatile memory cell includes a layered structure body formed by layering a storage layer that stores information in accordance with a magnetization direction and a magnetization fixed layer that defines a magnetization direction of the storage layer; and a heating layer that heats the magnetization fixed layer to control a magnetization direction of the magnetization fixed layer.

First claim

The invention claimed is:

1. A memory cell unit, comprising:
an array of a plurality of nonvolatile memory cells in a two-dimensional matrix in a first direction and a second direction different from the first direction,
wherein each nonvolatile memory cell of the plurality of nonvolatile memory cells comprises:
a layered structure body comprising:
a storage layer configured to store information based on a magnetization direction; and
a magnetization fixed layer configured to define the magnetization direction of the storage layer; and

a heating layer configured to:
heat the magnetization fixed layer; and
control a magnetization direction of the magnetization fixed layer based on the heated magnetization fixed layer, wherein

the heating layer includes at least a part of the magnetization fixed layer,
heating layers that constitute a respective nonvolatile memory cell of the plurality of nonvolatile memory cells are connected by heating layer extended portions respectively in a group of the plurality of nonvolatile memory cells arrayed along the first direction, and
the heating layer extended portions have a layer structure same as a layer structure of the heating layer.

2. The memory cell unit according to claim 1 , wherein the heating layer has a maximum width narrower than an average width of the heating layer extended portions.

3. The memory cell unit according to claim 1 , wherein the heating layer and the heating layer extended portions are configured to function as a bit line.

4. The memory cell unit according to claim 1 , further comprising an intermediate layer between the magnetization fixed layer and the storage layer, wherein
the magnetization fixed layer includes a layered structure in which a first fixed layer, a nonmagnetic layer, and a second fixed layer are layered from the intermediate layer side,
the first fixed layer and the second fixed layer have antiferromagnetic coupling, and
the first fixed layer has coercive force different from coercive force of the second fixed layer at a time the magnetization fixed layer is heated.

5. The memory cell unit according to claim 4 , wherein
the antiferromagnetic coupling between the first fixed layer and the second fixed layer is uncoupled by heating the magnetization fixed layer, and
a magnetization direction of the first fixed layer, a magnetization direction of the second fixed layer, and the magnetization direction of the storage layer become the same direction.

6. The memory cell unit according to claim 5 , wherein a magnetization direction of a fixed layer having larger coercive force out of the first fixed layer and the second fixed layer becomes the same direction as the magnetization direction of the storage layer.

7. The memory cell unit according to claim 1 , wherein each nonvolatile memory cell of the plurality of nonvolatile memory cells further includes a selection transistor including a field effect transistor.

8. The memory cell unit according to claim 7 , wherein the heating layer is further configured to generate heat based on current that flows in the heating layer in a state in which the selection transistor is inactivated.

9. The memory cell unit according to claim 7 , wherein the storage layer is connected to one of a source region or a drain region of the selection transistor.

10. The memory cell unit according to claim 7 , wherein a gate electrode of the selection transistor is connected to a word line.

11. The memory cell unit according to claim 1 , wherein each nonvolatile memory cell of the plurality of nonvolatile memory cells further includes a spin transfer torque based magnetic random access memory of a perpendicular magnetization type.

12. A nonvolatile memory cell, comprising:
a layered structure body comprising:
a storage layer configured to store information in based on a magnetization direction; and
a magnetization fixed layer configured to define the magnetization direction of the storage layer; and

a heating layer configured to:
heat the magnetization fixed layer; and
control a magnetization direction of the magnetization fixed layer, wherein
the heating layer includes at least a part of the magnetization fixed layer,
heating layers that constitute a respective nonvolatile memory cell of a plurality of nonvolatile memory cells are connected by heating layer extended portions respectively in a group of the plurality of nonvolatile memory cells arrayed along a first direction of an array of the plurality of nonvolatile memory cells, and
the heating layer extended portions have a layer structure same as a layer structure of the heating layer.

13. An information writing method in a memory cell unit, the information writing method comprising:
controlling a magnetization direction of a magnetization fixed layer by heating the magnetization fixed layer, wherein
the memory cell unit comprises an array of a plurality of nonvolatile memory cells in a two-dimensional matrix in a first direction and a second direction different from the first direction,
each nonvolatile memory cell of the plurality of nonvolatile memory cells comprises:
a layered structure body comprising the magnetization fixed layer and a storage layer configured to store information based on a magnetization direction of the storage layer; and
a heating layer configured to heat the magnetization fixed layer,

the magnetization fixed layer is configured to define the magnetization direction of the storage layer,
the heating layer includes at least a part of the magnetization fixed layer,
heating layers that constitute a respective nonvolatile memory cell of the plurality of nonvolatile memory cells are connected by heating layer extended portions respectively in a group of the plurality of nonvolatile memory cells arrayed along the first direction,
the heating layer extended portions have a layer structure same as a layer structure of the heating layer, and
the magnetization fixed layer is heated by making current flow in the heating layer and the heating layer extended portions; and

writing, in the storage layer, information based on the magnetization direction of the magnetization fixed layer.

14. The information writing method according to claim 13 , further comprising collectively writing first information by heating the magnetization fixed layer in the group of the plurality of nonvolatile memory cells arrayed along the first direction.

15. The information writing method according to claim 14 , further comprising:
stopping heating of the magnetization fixed layer by the heating layer after collectively writing the first information in the group of the plurality of nonvolatile memory cells arrayed along the first direction; and
writing second information in a desired nonvolatile memory cell in the group of the plurality of nonvolatile memory cells arrayed along the first direction.

16. An electronic apparatus, comprising:
a memory cell unit, wherein the memory cell unit comprises:
an array of a plurality of nonvolatile memory cells in a two-dimensional matrix in a first direction and a second direction different from the first direction,
wherein each nonvolatile memory cell of the plurality of nonvolatile memory cells comprises:
a layered structure body comprising:
a storage layer configured to store information based on a magnetization direction; and
a magnetization fixed layer configured to define the magnetization direction of the storage layer; and

a heating layer configured to:
heat the magnetization fixed layer; and
control a magnetization direction of the magnetizati

Assignees

• Sony Corp

Inventors

• Higo Yutaka
• Hosomi Masanori
• Ohmori Hiroyuki
• Bessho Kazuhiro
• Uchida Hiroyuki

Classifications

• H10D48/40

  Devices controlled by magnetic fields · CPC title

• H10D84/80

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H10N50/80

  Constructional details · CPC title

• H01F41/304

  using temporary decoupling, e.g. involving blocking, Néel or Curie temperature transitions by heat treatment in presence/absence of a magnetic field · CPC title