Display device

US10706773B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10706773-B2
Application numberUS-201715854060-A
CountryUS
Kind codeB2
Filing dateDec 26, 2017
Priority dateDec 28, 2016
Publication dateJul 7, 2020
Grant dateJul 7, 2020

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes a display area including a pixel array part, a connection area including a connection terminal part and a bending area including first and second connection lines disposed between the pixel array part and the connection terminal part. Each of the first connection line and the second connection line includes a first layer wiring on a first layer and a second layer wiring on a second layer different from the first layer, the first layer wiring being disposed obliquely and rightward to an extending direction of the first connection line and the second connection line, the second layer wiring being disposed obliquely and leftward to the extending direction and connected to the first layer wiring. The first layer wiring of the first connection line and the second layer wiring of the second connection line are disposed to intersect each other.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a display area including a pixel array part including at least one terminal; a connection area disposed on a back side of the display area and including a connection terminal part to which a signal is supplied from outside; and a bending area connecting the display area with the connection area and including a first connection line and a second connection line that are disposed between the pixel array part and the connection terminal part, wherein the pixel array part includes a transistor including a semiconductor layer, a first layer on the semiconductor layer, a gate electrode on the first layer, a second layer on the gate electrode, a source electrode on the second layer, and a drain electrode on the second layer, the first connection line includes a first wiring on the first layer and a second wiring on the second layer, the first wiring being disposed obliquely and leftward to an extending direction of the first connection line and the second connection line, the second wiring being disposed obliquely and rightward to the extending direction and connected to the first wiring, the second connection line includes a third wiring on the first layer and a fourth wiring on the second layer, the third wiring being disposed obliquely and leftward to the extending direction of the first connection line and the second connection line, the fourth wiring being disposed obliquely and rightward to the extending direction and connected to the third wiring, the first wiring and the third wiring are formed of a same layer as the gate electrode, the second wiring and the fourth wiring are formed of a same layer as the source electrode, the first wiring of the first connection line and the fourth wiring of the second connection line are disposed so as to intersect with each other, in plan view, the first wiring of the first connection line and the fourth wiring of the second connection line are overlapped each other, and the first wiring of the first connection line and the fourth wiring of the second connection line are separated from each other so that a predetermined insulation layer is disposed between the first wiring of the first connection line and the fourth wiring of the second connection line. 2. The display device according to claim 1 , further comprising a third connection line on the bending area, the third connection line disposed between the pixel array part and the connection terminal part, wherein the third connection line includes a fifth wiring and a sixth wiring, the fifth wiring of the third connection line is disposed between the first wiring of the first connection line and the third wiring of the second connection line, and intersects with the second wiring of the first connection line and the fourth wiring of the second connection line, the sixth wiring of the third connection line is disposed between the second wiring of the first connection line and the fourth wiring of the second connection line, and intersects with the first wiring of the first connection line and the third wiring of the second connection line, the fifth wiring and the third wiring are formed of a same layer as the gate electrode, the sixth wiring and the fourth wiring are formed of a same layer as the source electrode, in plan view, the fifth wiring of the third connection line overlaps with the fourth wiring of the second connection line and the second wiring of the first connection line, in plan view, the sixth wiring of the third connection line overlaps with the third wiring of the second connection line and the first wiring of the first connection line, the fifth wiring and the fourth wiring are separated from each other so that the predetermined insulation layer is disposed between the fifth wiring and the fourth wiring, the fifth wiring and the second wiring are separated from each other so that the predetermined insulation layer is disposed between the fifth wiring and the second wiring, the sixth wiring and the third wiring are separated from each other so that the predetermined insulation layer is disposed between the sixth wiring and the third wiring, and the sixth wiring and the first wiring are separated from each other so that the predetermined insulation layer is disposed between the sixth wiring and the first wiring. 3. The display device according to claim 1 , wherein the first connection line and the second connection line are electrically connected to each other in a frame area disposed around the display area and in the connection area. 4. The display device according to claim 2 , wherein the first to third connection lines are electrically connected to one another in a frame area disposed around the display area and in the connection area. 5. The display device according to claim 1 , wherein the first connection line receives one side of a differential signal, and the second connection line receives the other side of the differential signal. 6. The display device according to claim 2 , wherein GND voltage is supplied to the third connection line. 7. The display device according to claim 1 , wherein the first connection line includes a first connection wiring between the first layer and the second layer in an area where the first wiring overlaps with the second wiring, the first connection wiring electrically connecting the first wiring with the second wiring, and the second connection line includes a second connection wiring between the first layer and the second layer in an area where the third wiring overlaps with the fourth wiring, the second connection wiring electrically connecting the third wiring with the fourth wiring.

Assignees

Inventors

Classifications

  • using coherent electromagnetic radiation, e.g. laser annealing · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

  • Insulating layers formed between TFT elements and OLED elements · CPC title

  • comprising a multilayered structure · CPC title

Patent family

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Frequently asked questions

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What does patent US10706773B2 cover?
A display device includes a display area including a pixel array part, a connection area including a connection terminal part and a bending area including first and second connection lines disposed between the pixel array part and the connection terminal part. Each of the first connection line and the second connection line includes a first layer wiring on a first layer and a second layer wirin…
Who is the assignee on this patent?
Japan Display Inc
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 07 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).