Analog circuit fault mode classification method

Patent metadata

Field	Value
Publication number	US-10706332-B2
Application number	US-201515555077-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Aug 7, 2015
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

An analog circuit fault mode classification method comprises the following implementation steps: (1) collecting M groups of voltage signal sample vectors Vij to each of fault modes Fi of the analog circuit by using a data collection board; (2) sequentially extracting fault characteristic vectors VijF of the voltage signal sample vectors Vij by using subspace projection; (3) standardizing the extracted fault characteristic vectors VijF to obtain standardized fault characteristic vectors; (4) constructing a fault mode classifier based on a support vector machine, inputting the standardized fault characteristic vectors, performing learning and training on the classifier, and determining structure parameters of the classifier; and (5) completing determination of fault modes according to fault mode determination rules. The fault mode classifier of the present invention is simple in learning and training and reliable in mode classification accuracy.

First claim

What is claimed is:

1. An analog circuit fault mode classification method, comprising:
(1) collecting M groups of voltage signal sample vectors V ij at a node to be tested under each of fault modes F i of the analog circuit by using a data collection board, wherein j=1, 2, . . . , M, i=1, 2, . . . , N, V ij represents a j th voltage signal sample vector of a i th fault mode, and N represents a total number of the fault modes;
(2) sequentially extracting fault characteristic vectors V ij F of the voltage signal sample vectors V ij working under the fault modes F i by using subspace projection, wherein i=1, 2, . . . , N, j=1, 2, . . . , M, and V ij F represents a fault characteristic vector of the j th voltage signal sample under the i th fault mode;
(3) standardizing the extracted fault characteristic vectors V ij F to obtain standardized fault characteristic vectors {circumflex over (V)} ij F , wherein a computing method for obtaining the standardized fault characteristic vectors is

V
^

ij
F

=

V
ij
F



V
ij
F



;

(4) sequentially constructing a binary-class support vector machine with respect to two different fault modes F i 1 and F i 2 , wherein i 1 =1, 2, . . . , N, i 2 =1, 2, . . . , N, and i 1 ≠i 2 , N is the total number of the fault modes, then N(N−1)/2 different binary-class support vector machines can be constructed in total; and
(5) classifying a standardized fault characteristic vectors to be tested to obtain a classification result by simultaneously feeding a standardized fault characteristic to be tested into the N(N−1)/2 binary-class support vector machines in response to the fault mode to be tested is classified to the fault mode F i by the binary-class support vector machine and i=1, 2, . . . , N, adding 1 to the votes of the fault mode F i , and, determining the fault modes having most votes is a circuit to be tested belongs to.

2. The analog circuit fault mode classification method according to claim 1 , wherein the step of extracting the fault characteristic vectors V ij F by using the subspace projection in step (2) comprises:
(2.1) computing dimensionality L of the voltage signal sample vectors V ij : L=length(V ij );
(2.2) generating an L×L dimensional Toeplitz transformation matrix Φ:

Φ
=

[

F
11

F
12

…

F

1
⁢
L

F
12

F
13

…

F
11

…

…

…

…

F

1
⁢
L

F
11

…

F

1
⁢

(

L
-
1

)

]

,
wherein

F

1
⁢
k

=

e

-
j

⁢

2
⁢
π

L

⁢
k

,

k
=
1

,
2
,
…
⁢

,

L
;

(2.3) computing a projected vector of the voltage signal sample vectors V ij in the Toeplitz transformation matrix Φ: V p =Φ T V ij , wherein T represents to transpose a matrix;
(2.4) computing maximum projection subspace and the fault characteristic vectors V ij F :
(2.4.1) initializing a subspace projection coordinate dimensionality K: K=┌log 2 (N)┐, wherein ┌⋅┐ represents rounding up to an integer, and N is the total number of the fault modes of the circuit to be tested;
(2.4.2) constructing a maximum projection subspace index vector I with a dimensionality of 1×K, and initializing the maximum projection subspace index vector into a 1×K dimensional null vector, i.e., I=[0 0 . . . 0], and meanwhile constructing a counting variable p

Assignees

• Univ Hefei Technology

Inventors

• Yuan Lifen
• Luo Shuai
• He Yigang
• Chen Peng
• Zhang Chaolong
• Long Ying
• Cheng Zhen
• Yuan Zhijie
• Zhao Deqin

Classifications

• G06F2218/12

  Classification; Matching · CPC title

• G06F2218/08

  Feature extraction · CPC title

• G06F18/2411 Primary

  based on the proximity to a decision surface, e.g. support vector machines · CPC title

• G01R31/316 Primary

  Testing of analog circuits {(G01R31/2851 takes precedence)} · CPC title

• G06F18/2135

  based on approximation criteria, e.g. principal component analysis · CPC title