Current sensor based closed loop control apparatus

Patent metadata

Field	Value
Publication number	US-10705559-B2
Application number	US-201816189973-A
Country	US
Kind code	B2
Filing date	Nov 13, 2018
Priority date	Jun 26, 2015
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.

First claim

We claim:

1. An apparatus comprising:
a power control unit (PCU); and
a plurality of cores coupled to the PCU, each core of the plurality of cores comprising
one or more current sensors, and
a controller coupled to the one or more current sensors to compare a sensed current with a target current from the PCU, and

wherein the PCU is configured to adjust the target current based on an amount of throttling being performed by the plurality of cores.

2. The apparatus defined in claim 1 wherein the PCU is operable to increase the target current of one of the plurality of cores in response to the amount of throttling.

3. The apparatus defined in claim 2 wherein the PCU is operable to increase the target current of the one core of the plurality of cores to cause less throttling.

4. The apparatus defined in claim 1 wherein the controller is operable to control an amount of current received by said each core by changing a first clock signal of said each core.

5. The apparatus defined in claim 4 wherein changing the first clock signal of said each core comprises generating a second clock signal by removing pulses of the first clock signal to create the second clock signal.

6. A method comprising:
measuring current in a plurality of cores, using current sensors, coupled to a power control unit (PCU), the current sensors being in the plurality of cores, where each core of the plurality of cores comprises one or more current sensors;
comparing a sensed current with a target current from the PCU; and
adjusting the target current based on an amount of throttling being performed by the plurality of cores.

7. The method defined in claim 6 further comprising increasing the target current of one of the plurality of cores in response to the amount of throttling.

8. The method defined in claim 6 wherein adjusting the target current based on an amount of throttling comprises causing less throttling.

9. The method defined in claim 6 further comprising controlling an amount of current received by said each core by changing a first clock signal of said each core.

10. The method defined in claim 9 wherein changing the first clock signal of said each core comprises generating a second clock signal by removing pulses of the first clock signal to create the second clock signal, and further comprising providing the second clock signal to said each core.

11. The article of manufacture defined in claim 9 wherein changing the first clock signal of said each core comprises generating a second clock signal by removing pulses of the first clock signal to create the second clock signal, and further comprising providing the second clock signal to said each core.

12. An article of manufacture having one or more non-transitory computer readable storage media storing instructions which when executed by a system to perform a method comprising:
measuring current in a plurality of cores, using current sensors, coupled to a power control unit (PCU), the current sensors being in the plurality of cores, where each core of the plurality of cores comprises one or more current sensors;
comparing a sensed current with a target current from the PCU; and
adjusting the target current based on an amount of throttling being performed by the plurality of cores.

13. The article of manufacture defined in claim 12 wherein the method further comprises increasing the target current of one of the plurality of cores in response to the amount of throttling.

14. The article of manufacture defined in claim 12 wherein adjusting the target current based on an amount of throttling comprises causing less throttling.

15. The article of manufacture defined in claim 12 wherein the method further comprises controlling an amount of current received by said each core by changing a first clock signal of said each core.

Assignees

• Intel Corp

Inventors

• Gendler Alexander
• Luria Kosta
• Albahari Arye
• Nachshon Ohad

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G01R19/16533

  characterised by the application · CPC title

• G01R19/0092

  Measuring current only · CPC title

• G01R19/16528

  using digital techniques or performing arithmetic operations (using digital techniques to measure a voltage or a current, see G01R19/25) · CPC title