Touch display panel having touch line formed on the same layer as the gate line

Patent metadata

Field	Value
Publication number	US-10705367-B2
Application number	US-201816180419-A
Country	US
Kind code	B2
Filing date	Nov 5, 2018
Priority date	Feb 1, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

An array substrate includes a base substrate, a plurality of first signal lines extending in a first direction, a plurality of second signal lines located on a different layer from the first signal lines and extending in a second direction intersecting the first direction, and a plurality of touch signal lines extending in the second direction disposed on the base substrate. Each touch signal line includes a first touch line segment and a second touch line segment, the first touch line segment disposed on the same layer as the first signal lines, and at least partially overlapping with at least one of the second signal lines in a direction perpendicular to a surface of the base substrate, the second touch line segment disposed on a different layer from the first signal lines, and the first touch line segment electrically connected with the second touch line segment through a first via.

First claim

The invention claimed is:

1. An array substrate, comprising:
a base substrate;
a plurality of first signal lines, disposed on the base substrate and extending in a first direction;
a plurality of second signal lines, disposed on the base substrate and located on a different layer from the first signal lines, and extending in a second direction intersecting the first direction;
a plurality of touch signal lines, disposed on the base substrate and extending in the second direction;
a second insulating layer, covering the second signal line;
a common electrode, disposed on the second insulating layer;
a third via, penetrating the second insulating layer,
wherein each of the touch signal lines comprises a first touch line segment and a second touch line segment, the first touch line segment is disposed on the same layer as the first signal lines, and is at least partially overlapped with at least one of the second signal lines in a direction perpendicular to a surface of the base substrate, the second touch line segment is disposed on a different layer from the first signal lines, and the first touch line segment and the second touch line segment are electrically connected with each other through a first via,
the first signal line is a gate line configured to transmit a gate signal; and the second signal line is a display data line configured to transmit a display data signal, and
the common electrode comprises a plurality of sub-electrodes acting as touch electrodes in a multiplexing manner, each of the plurality of sub-electrodes is electrically connected with a corresponding touch signal line via the third via.

2. The array substrate according to claim 1 , further comprising a plurality of dummy signal lines disposed on the base substrate and extending in the second direction;
wherein each of the dummy signal lines comprises a first dummy line segment and a second dummy line segment, the first dummy line segment is disposed on the same layer as the first signal lines and is at least partially overlapped with at least one of the second signal lines, which is not overlapped with the touch signal lines, in the direction perpendicular to the surface of the base substrate, the second dummy line segment is disposed on a different layer from the first signal lines, and the first dummy line segment and the second dummy line segment are electrically connected with each other through a second via.

3. The array substrate according to claim 1 , further comprising a first insulating layer, wherein the first insulating layer covers the gate line, the first via penetrates the first insulating layer, and the second touch line segment is located on the same layer as the display data line and is disposed on the first insulating layer.

4. The array substrate according to claim 1 , wherein the touch signal lines do not overlap with a gap region of the plurality of sub-electrodes in the first direction.

5. The array substrate according to claim 1 , wherein the third via and a gap region between the plurality of sub-electrodes do not overlap with each other.

6. The array substrate according to claim 1 , wherein a plurality of adjacent touch signal lines are electrically connected with each other through a connection portion which is located on a same layer as the first touch line segment and extends in the first direction.

7. The array substrate according to claim 1 , further comprising a plurality of sub-pixels defined by intersections of the first signal lines and the second signal lines, wherein each sub-pixel comprises a thin film transistor as a switching element, the first touch line segment or the second touch line segment does not overlap with the thin film transistor in the direction perpendicular to the surface of the base substrate.

8. The array substrate according to claim 1 , wherein the touch signal line is a metal signal line.

9. A touch display panel, comprising the array substrate according to claim 1 .

10. The touch display panel according to claim 9 , wherein the touch display panel is a liquid crystal display panel.

11. A manufacturing method of an array substrate, comprising:
forming, on a base substrate, a plurality of first signal lines extending in a first direction and first touch line segments of a plurality of touch signal lines extending in a second direction intersecting the first direction;
forming, on the plurality of first signal lines and the first touch line segments, a plurality of second signal lines extending in the second direction and second touch line segments of a plurality of touch signal lines extending in the second direction;
forming a second insulating layer to cover the second signal line;
forming a common electrode on the second insulating layer;
forming a third via that penetrates the second insulating layer,
wherein the first touch line segments are located on a same layer as the first signal lines, and at least partially overlap with at least one of the second signal lines in a direction perpendicular to a surface of the base substrate, the second touch line segments are located at a different layer from the first signal lines, and the first touch line segments and the second touch line segments are electrically connected through the first via,
the first signal line is a gate line configured to transmit a gate signal; and the second signal line is a display data line configured to transmit a display data signal, and
the common electrode comprises a plurality of sub-electrodes acting as touch electrodes in a multiplexing manner, each of the plurality of sub-electrodes is electrically connected with a corresponding touch signal line via the third via.

12. The array substrate according to claim 2 , further comprising a first insulating layer, wherein the first insulating layer covers the gate line, the first via penetrates the first insulating layer, and the second touch line segment is located on the same layer as the display data line and is disposed on the first insulating layer.

13. The array substrate according to claim 2 , wherein the touch signal lines do not overlap with a gap region of the plurality of sub-electrodes in the first direction.

14. The array substrate according to claim 2 , wherein the third via and a gap region between the plurality of sub-electrodes do not overlap with each other.

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Wang Zhengkui
• Sun Jian
• Huang Fei
• Wang Jiguo
• Qiao Yun
• Zhan Xiaozhou
• Zhang Han
• Wang Zhen
• Qin Wenwen
• Cong Lele
• Liu Peng
• Zhang Jianjun

Classifications

• G02F1/13338 Primary

  Input devices, e.g. touch panels · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G06F3/0443

  using a single layer of sensing electrodes · CPC title

• G06F3/04164 Primary

  Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title