Transmission device, transmission method, receiving device and receiving method
US-2015381256-A1 · Dec 31, 2015 · US
US10700897B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10700897-B2 |
| Application number | US-201615358164-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 22, 2016 |
| Priority date | Jun 10, 2011 |
| Publication date | Jun 30, 2020 |
| Grant date | Jun 30, 2020 |
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Highly efficient digital domain sub-band based receivers and transmitters.
Opening claim text (preview).
We claim: 1. A receiver that comprises: a first serial to parallel converter arranged to receive first digital signals that represent optical signals of a first polarity, and to output the first digital signals via multiple outputs; a first polyphase finite impulse response (FIR) filter array coupled between the first serial to parallel converter and to a first inverse fast Fourier transform (IFFT) module; a second serial to parallel converter arranged to receive second digital signals that represent optical signals of a second polarity, and to output the second digital signals via multiple outputs; a second polyphase finite impulse response (FIR) filter array coupled between the second serial to parallel converter and to a second (IFFT) module; multiple sub-band processor modules; wherein each sub-band processor module is coupled to inputs of a same order of the first and second IFFT modules; wherein the sub-band processor modules are Orthogonal Frequency Division Multiplex (OFDM) sub-band receiver modules; and wherein the receiver comprises a de-mapper and a data multiplexor that follows the multiple OFDM sub-band receiving modules. 2. A receiver that comprises: a first serial to parallel converter arranged to receive first digital signals that represent optical signals of a first polarity, and to output the first digital signals via multiple outputs; a first polyphase finite impulse response (FIR) filter array coupled between the first serial to parallel converter and to a first inverse fast Fourier transform (IFFT) module; a second serial to parallel converter arranged to receive second digital signals that represent optical signals of a second polarity, and to output the second digital signals via multiple outputs; a second polyphase finite impulse response (FIR) filter array coupled between the second serial to parallel converter and to a second (IFFT) module; multiple sub-band processor modules; wherein each sub-band processor module is coupled to inputs of a same order of the first and second IFFT modules; and a coherent optical front end and two pairs of analog to digital converters (ADCs); wherein the coherent optical front end is arranged to: receive the optical signals of the first and second polarity; provide analog signals representative of the optical signals of the first polarization to a first pair of ADCs, and provide analog signals representative of the optical signals of the second polarization to a second pair of ADCs; wherein the first pair of ADCs is coupled to the first serial to parallel converter; and wherein the second pair of ADCs is coupled to the second serial to parallel converter. 3. The receiver according to claim 1 , wherein each OFDM sub-band receiving module comprises: two sequentially coupled sets of components, each sequentially coupled set of components comprises a sub-band impairment compensator, a serial to parallel conversion and cyclic prefix drop module, a 2N-points fast Fourier transform (FFT) module and a half band decimator; a pair of parallel to parallel converters; a plurality of dual input dual output (2×2 MIMO) equalization modules, wherein different pairs of outputs of the half band decimators for the two polarizations are coupled to pairs of inputs of different 2×2 MIMO equalization modules; wherein each 2×2 MIMO equalization module comprises a pair of outputs that are coupled to inputs of a same order of the pair of parallel to parallel converters; and a pair of carrier recovery and decision modules, each carrier recovery and decision module is coupled to a parallel to parallel converter of the pair of parallel to parallel converters. 4. The receiver according to claim 1 wherein the sub-band processors comprise two sequentially coupled sets of components, each sequentially coupled set of components comprises a sub-band impairment compensator, a serial to parallel conversion and cyclic prefix drop module, a 2N-points Fast Fourier transform (FFT) module and a half band decimator; a pair of parallel to parallel converters; a plurality of dual input dual output (2×2 MIMO) equalization modules, wherein different pairs of outputs of a same order of the half band decimators for the two polarizations are coupled to pairs of inputs of different 2×2 MIMO equalization modules; wherein each 2×2 MIMO equalization module comprises a pair of outputs that are coupled to inputs of a same order of the pair of parallel to parallel converters. 5. The receiver according to claim 4 wherein the carrier recovery and decision modules are multiple-symbol differential detection (MSDD) decoders. 6. The receiver according to claim 4 wherein each sub-band impairment compensator comprises the cascade of an in-phase quadrature imbalance (IQI) compensator, a mixer and a delay unit. 7. The receiver according to claim 4 wherein each sub-band impairment compensator comprises a cascade of an in-phase quadrature imbalance (IΩI) compensator, a mixer and a delay unit. 8. The receiver according to claim 4 wherein the half-band decimator is filterless, and is arranged to route an N-points input either into a high or a low half-band of N points out of 2N inputs, dropping the remaining N points. 9. The receiver according to claim 7 wherein the half-band decimator is filterless, and is arranged to route a N points input either into a high or a low half-band of N points out of its 2N inputs, dropping the remaining N points. 10. The receiver according to claim 4 wherein the half-band decimator is arranged to perform a cyclic shift for odd numbered sub-band indexes module. 11. The receiver according to claim 7 wherein the half-band decimator is arranged to perform a cyclic shift for odd numbered sub-band indexes module. 12. The receiver according to claim 4 wherein the sub-band processors are arranged to feed an array of 2Nssc IFFT modules wherein Nssc IFFT modules form a sub-array corresponding to X polarization of signals and Nssc IFFT modules form a sub-array correspond to Y polarization of signals; the number Nssc divides the number P of sub-band processors; The sub-band processors are partitioned into P/Nssc groups; the X-outputs of the sub-band processors in the g-th group are uniformly spread onto the inputs of the g-th IFFT in the X sub-array via serial to parallel converters; the Y-outputs of the sub-band processors in the g-th group are uniformly spread onto the g-th IFFT in the Y sub-array via serial to parallel converters; the number of output ports of the serial to parallel converters used to perform the spreadings is given by the IFFT size divided by the number of sub-band processors. 13. The receiver according to claim 12 wherein each sub-band processor module comprises: two sequentially coupled sets of components, each sequentially coupled set of components comprises a sub-band impairment compensator, a serial to parallel conversion and cyclic prefix drop module, a 2N-points fast Fourier transform (FFT) module and a half band decimator; a pair of parallel to parallel converters; a plurality of dual input dual output (2×2 MIMO) equalization modules, wherein different pairs of outputs of the half band decimators for the two polarizations are coupled to pairs of inputs of different 2×2 MIMO equalization modules; wherein each 2×2 MIMO equalization module comprises a pair of outputs that are coupled to inputs of a same order of the pair of parallel to parallel converters. 14. The receiver according to claim 4 , further comprising a joint IQI, Carrier Frequency Offset (CFO), Coarse Timing Offset (CTO), Sampling Frequency Offset (SFO) estimation module that is coupled to the mixer and to the delay unit
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