Analog-digital converter, semiconductor device, and voltage signal generation method

Patent metadata

Field	Value
Publication number	US-10700693-B2
Application number	US-201916412030-A
Country	US
Kind code	B2
Filing date	May 14, 2019
Priority date	Jun 19, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

The analog-to-digital converter includes a quantizer for outputting a quantized signal, a sampling circuit for sampling an analog input signal, a dithering circuit for generating an added voltage, and an integrating circuit for integrating a signal on which the added voltage is superimposed and outputting an integration result to the quantizer. The dithering circuit includes a variable capacitance circuit and a control circuit. The variable capacitance circuit includes a plurality of capacitors. The control circuit controls the capacitance of the variable capacitance circuit to a capacitance smaller than the capacitances of the capacitors, and causes the variable capacitance circuit to generate an added voltage.

First claim

What is claimed is:

1. An analog digital converter comprising:
a quantizer quantizing input signal and outputting the quantized signal,
a sampling circuit sampling analog input signal and output differential signal according to difference between the sampled analog input signal and a feedback signal corresponding to the quantized signal,
a dithering circuit generating additional voltage,
an integrating circuit integrating signal which the differential signal and the additional voltage is added, and outputting signal to the quantizer,
wherein the dithering circuit comprises;
a capacitance circuit comprising plurality of capacitors,
a control circuit for making the capacitance circuit output the additional voltage, while controlling the capacitance of the capacitance circuit to keep it smaller than the biggest capacitance of the plurality of the capacitors.

2. An analog digital converter according claim 1 ,
wherein each capacitor of the plurality of capacitors is connected to each other in series between an input node and output node of the capacitance circuit,
and wherein the control circuit for making the capacitance circuit output the additional voltage with a predetermined number of the capacitors from the plurality of capacitors.

3. An analog digital converter according to claim 2 ,
wherein the sampling circuit outputs the differential signal according to difference between the analog signal and the feedback signal, within an integration period which the integrating circuit integrates the differential signal,
wherein the control circuit makes the predetermined numbers of capacitors sample predetermined voltage within a sampling period when the sampling circuit samples the analog input signal, and making the predetermined numbers of capacitors output the additional voltage corresponding to the predetermined voltage within the integration period.

4. An analog digital converter according to claim 3 ,
wherein the control circuit makes the predetermined numbers of capacitors sample voltage of difference between third reference voltage of the output node and one of first reference voltage and second reference voltage that are inputted to the input node within the sampling period, and making the predetermined numbers of capacitors output the additional voltage corresponding to the other of first reference voltage and the second reference voltage that are inputted to the input node within the integration period.

5. An analog digital converter according to claim 4 ,
the capacitance circuit further comprising plurality of capacitors changing switch arranged between the input node and input node side terminals of the plurality of capacitors respectively,
when n is an integer of describing number of the capacitors which are used for generating the additional voltage,
wherein the control circuit makes the capacitor changing switches arranged between the input node and input node side terminal of the capacitor that is n order which is count number of the capacitor from the most input node side on, and making other remaining capacitors changing switches off, within both the sampling period and integration period.

6. An analog digital converter according to claim 4 ,
the dithering circuit further comprising,
first voltage changing switch arranged between a terminal of the first reference voltage and the input node of the capacitance circuit, and
second voltage changing switch arranged between a terminal of the second reference voltage and the input node of the capacitance circuit,
wherein the control circuit makes one of the first voltage changing switch and second voltage changing switch on and other of the first voltage changing switch and second voltage changing switch off within sampling period, and making the other of the first voltage changing switch and second voltage changing switch on and the one of the first voltage changing switch and second voltage changing switch off within integration period.

7. An analog digital converter according to claim 4 ,
wherein the first reference voltage and the second reference voltage are changed predetermined fourth voltage and predetermined fifth voltage alternatively, the second reference voltage is the fifth voltage when the first reference voltage is the fourth voltage, and the second reference voltage is the fifth voltage when the first reference voltage is the fourth voltage.

8. An analog digital converter according to claim 4 ,
the capacitance circuit further comprising plurality of initialization switch which are arranged between a terminal of predetermined initialization voltage and input node side terminals of the plurality of capacitors respectively,
the control circuit turns on the plurality of initialization switch at timing of operation of the capacitance circuit start.

9. An analog digital converter according to claim 8 ,
wherein the initialization voltage being the third reference voltage, and
the control circuit turns on the plurality of initialization switch while the output node of the capacitance circuit being connected to the third reference voltage.

10. An analog digital converter according to claim 1 ,
wherein each capacitance of the plurality of capacitors being equal to each other.

11. An analog digital converter according to claim 1 ,
wherein the plurality of capacitors being connected in parallel each other,
wherein the control circuit makes the capacitance circuit outputs the additional voltage, by making predetermined numbers of capacitors, which is in the plurality of the capacitors, sample predetermined voltage, distributing charge which is stored by the predetermined number of capacitors to the whole of the plurality of capacitor, and making one of the pluralities of capacitors output charge which is distributed according to the control circuit.

12. An analog digital converter according to claim 11 ,
wherein the sampling circuit outputting the differential signal which is difference between the analog input signal and the feedback signal, within a period when the integrating circuit is integrating the differential signal,
wherein the control circuit makes the capacitance circuit sample the predetermined voltage in a sampling period when the sampling circuit samples the analog input circuit, making the capacitance circuit distribute charge which is integrated from the sampling period to the integration period, and making the capacitance circuit output charge which is distributed within the integration period.

13. An analog digital converter according to claim 11 ,
wherein the control circuit makes the predetermined number of capacitors sample differential voltage which is the difference between the third reference voltage and one of the second reference voltage and the first reference voltage which is inputted from the input node of the capacitance circuit.

14. An analog digital converter according to claim 11 ,
the capacitance circuit further comprising a plurality of parallel number control switches, one side terminals of the plurality of capacitors being connected to an node of third reference voltage, one of the plurality of parallel number control switches being connected between the other side terminal of one capacitor of the plurality of capacitors and the other side of terminal of another capacitor, which is next to the one capacitor, of the plurality of capacitors, respectively,
wherein i is an integer of predetermined number,
wherein at the sampling of the predetermined voltage, the control circuit controlling the parallel number control switches, which are arranged between from first order of the capacitor correspondin

Assignees

• Renesas Electronics Corp

Inventors

• Watanabe Akemi

Classifications

• H03M3/456

  the modulator having a first order loop filter in the feedforward path · CPC title

• H03M1/442

  using switched capacitors · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title

• H03M1/0648 Primary

  by arranging the quantisation value generators in a non-sequential pattern layout, e.g. symmetrical · CPC title

• H03M3/328 Primary

  using dither · CPC title