Wideband low noise amplifier having DC loops with back gate biased transistors

Patent metadata

Field	Value
Publication number	US-10700653-B2
Application number	US-201815959514-A
Country	US
Kind code	B2
Filing date	Apr 23, 2018
Priority date	Apr 23, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.

First claim

What is claimed is:

1. An amplifier device circuit structure comprising:
a first amplifier device, wherein the first amplifier device inverts and amplifies an input signal to produce an intermediate signal;
a second amplifier device, wherein the second amplifier device is connected to an input of the first amplifier device and inverts and amplifies the input signal to produce an amplified inverted output signal;
a third amplifier device connected to an output of the first amplifier device, wherein the third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal; and
a feedback loop connected to the output of the first amplifier device and to the input of the first amplifier device,
wherein the first amplifier device, the second amplifier device, and the third amplifier device each include a direct current (DC) loop circuit that includes biased transistors, and
wherein each of the biased transistors has a back gate connected to at least one reference device that generates a bias current.

2. The amplifier device circuit structure according to claim 1 , wherein the first amplifier device further comprises a first transistor connected to ground to set bias current to the first amplifier device,
wherein the second amplifier device further comprises a second transistor connected to ground to set bias current to the second amplifier device,
wherein the third amplifier device further comprises a third transistor connected to ground to set bias current to the third amplifier device, and
wherein the first transistor, the second transistor, and the third transistor are connected to the at least one reference device that generates the bias current.

3. The amplifier device circuit structure according to claim 2 , wherein the bias current is connected to the back gate of the first transistor, the second transistor, and the third transistor.

4. The amplifier device circuit structure according to claim 2 , wherein the bias current supplied to the first transistor, the second transistor, and the third transistor is different for each different transistor.

5. The amplifier device circuit structure according to claim 2 , wherein the first amplifier device further comprises a first complementary transistor connected to a voltage source,
wherein the first complementary transistor is of opposite polarity to the first transistor,
wherein the second amplifier device further comprises a second complementary transistor connected to the voltage source,
wherein the second complementary transistor is of opposite polarity to the second transistor,
wherein the third amplifier device further comprises a third complementary transistor connected to the voltage source, and
wherein the third complementary transistor is of opposite polarity to the third transistor.

6. The amplifier device circuit structure according to claim 5 , wherein the at least one reference device is connected to the first transistor, the second transistor, and the third transistor, wherein the reference device generates the bias current at a mid-supply voltage that is between the voltage source and ground.

7. The amplifier device circuit structure according to claim 6 , wherein the feedback loop includes a resistor, and wherein the resistor maintains gates of the first amplifier device at the mid-supply voltage, and the first amplifier device maintains gates of the second amplifier device and the third amplifier device at the mid-supply voltage.

8. An amplifier device circuit structure comprising:
a first amplifier device, wherein the first amplifier device inverts and amplifies an input signal to produce an intermediate signal;
a second amplifier device, wherein the second amplifier device is connected to an input of the first amplifier device and inverts and amplifies the input signal to produce an amplified inverted output signal;
a third amplifier device connected to an output of the first amplifier device, wherein the third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal; and
a feedback loop connected to the output of the first amplifier device and to the input of the first amplifier device, and wherein the feedback loop includes a resistor, wherein a gain ratio of a gain of the third amplifier device to a gain of the second amplifier device matches a resistance ratio of a source resistance of the input signal to a resistance of the resistor added to the source resistance,
wherein the first amplifier device, the second amplifier device, and the third amplifier device each include a direct current (DC) loop circuit that includes biased transistors, and
wherein each of the biased transistors has a back gate connected to at least one reference device that generates a bias current.

9. The amplifier device circuit structure according to claim 8 , wherein the first amplifier device further comprises a first transistor connected to ground to set bias current to the first amplifier device,
wherein the second amplifier device further comprises a second transistor connected to ground to set bias current to the second amplifier device,
wherein the third amplifier device further comprises a third transistor connected to ground to set bias current to the third amplifier device, and
wherein the first transistor, the second transistor, and the third transistor are connected to the at least one reference device that generates the bias current.

10. The amplifier device circuit structure according to claim 9 , wherein the bias current is connected to the back gate of the first transistor, the second transistor, and the third transistor.

11. The amplifier device circuit structure according to claim 9 , wherein the bias current supplied to the first transistor, the second transistor, and the third transistor is different for each different transistor.

12. The amplifier device circuit structure according to claim 9 , wherein the first amplifier device further comprises a first complementary transistor connected to a voltage source,
wherein the first complementary transistor is of opposite polarity to the first transistor,
wherein the second amplifier device further comprises a second complementary transistor connected to the voltage source,
wherein the second complementary transistor is of opposite polarity to the second transistor,
wherein the third amplifier device further comprises a third complementary transistor connected to the voltage source, and
wherein the third complementary transistor is of opposite polarity to the third transistor.

13. The amplifier device circuit structure according to claim 12 , wherein the at least one reference device is connected to the first transistor, the second transistor, and the third transistor, wherein the reference device generates the bias current at a mid-supply voltage that is between the voltage source and ground.

14. The amplifier device circuit structure according to claim 13 , wherein the resistor maintains gates of the first amplifier device at the mid-supply voltage, and the first amplifier device maintains gates of the second amplifier device and the third amplifier device at the mid-supply voltage.

15. A method of forming an amplifier device circuit structure comprising:
forming a first amplifier device connected to invert and amplify an input signal, and to produce an intermediate signal;
forming a second amplifier device connected to an input of the first amplifier device and invert and ampl

Assignees

• Globalfoundries Inc

Inventors

• Manetakis Konstantinos
• Mckay Thomas G

Classifications

• H03F2203/45356

  the AAC comprising one or more op-amps, e.g. IC-blocks · CPC title

• H03F3/45269

  Complementary non-cross coupled types · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title