Mixer bias circuit

Patent metadata

Field	Value
Publication number	US-10700641-B1
Application number	US-201916729548-A
Country	US
Kind code	B1
Filing date	Dec 30, 2019
Priority date	Jan 2, 2019
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

The present invention discloses a mixer bias circuit including a first reference voltage generation circuit, an amplifier, a first transistor array, a first switch array, a second reference voltage generation circuit, a second transistor array, a second switch array, a first resistive component, and a second resistive component. The mixer bias circuit provides multiple bias voltages by dynamically tracking the common mode voltage of a trans-impedance amplifier (TIA) and compensates for imbalance and mismatch effects by asymmetrically trimming the bias voltages to improve the second-order intercept point of a radio frequency (RF) receiver front-end (RXFE).

First claim

What is claimed is:

1. A mixer bias circuit applied to a radio frequency (RF) receiver front-end (RXFE), the RF RXFE including a mixer and a trans-impedance amplifier (TIA), the mixer bias circuit having a first output terminal, a second output terminal, and a third output terminal that respectively output a first bias voltage, a second bias voltage, and a third bias voltage, the mixer bias circuit comprising:
a first reference voltage generation circuit configured to generate a reference voltage according to a common-mode voltage of the TIA;
an amplifier that is coupled to the first reference voltage generation circuit and that has a first input terminal for receiving the reference voltage, a second input terminal coupled to the second output terminal and for receiving the second bias voltage, and an output terminal;
a first transistor array including a plurality of first transistors;
a first switch array coupled between the first transistor array and the first output terminal and including a plurality of first switches, wherein a total number of the first switches that are to be turned on is based on a calibration code;
a second reference voltage generation circuit;
a second transistor array including a plurality of second transistors coupled to the second reference voltage generation circuit;
a second switch array coupled between the second transistor array and the third output terminal and including a plurality of second switches, wherein a total number of the second switches that are to be turned on is based on the calibration code;
a first resistive component coupled between the first output terminal and the second output terminal and having a first resistance; and
a second resistive component coupled between the second output terminal and the third output terminal and having a second resistance.

2. The mixer bias circuit of claim 1 , wherein the first transistors are in one-to-one correspondence with the first switches, and the second transistors are in one-to-one correspondence with the second switches.

3. The mixer bias circuit of claim 2 , wherein a total number of the first switches is equal to a total number of the second switches, and a total number of the first switches that are turned on is equal to a total number of the second switches that are turned on.

4. The mixer bias circuit of claim 2 , wherein sources of the first switches are coupled to drains of the corresponding first transistors, gates of the first switches receive the calibration code, and drains of the first switches are coupled to the first output terminal; sources of the second switches are coupled to drains of the corresponding second transistors, gates of the second switches receive the calibration code, and drains of the second switches are coupled to the third output terminal.

5. The mixer bias circuit of claim 1 , wherein a total number of the first switches is equal to a total number of the second switches.

6. The mixer bias circuit of claim 1 further comprising:
a third resistive component having a third resistance; and
a capacitor;
wherein the third resistive component and the capacitor are connected in series between the output terminal of the amplifier and the first output terminal.

7. The mixer bias circuit of claim 1 , wherein gates of the first transistors are coupled to the output terminal of the amplifier, and gates of the second transistors receive a bias voltage that the second reference voltage generation circuit provides.

Assignees

• Realtek Semiconductor Corp

Inventors

• Chan Ka-Un
• Yeh Rong-Fu
• Wu Chao-Huang

Classifications

• H03D7/1425 Primary

  with transistors · CPC title

• H04B1/30

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title

• H03F3/347

  in integrated circuits · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title