Circuit and system implementing a power supply configured for spark prevention

Patent metadata

Field	Value
Publication number	US-10700603-B2
Application number	US-201816113417-A
Country	US
Kind code	B2
Filing date	Aug 27, 2018
Priority date	Dec 13, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A circuit comprises a primary transistor connecting a primary voltage source to a load connector. A translator and a secondary transistor cause opening of the primary transistor when receiving an off command and cause closing of the primary transistor when receiving an on command. The secondary transistor is powered by a secondary voltage source. A microcontroller receives measurements of a load voltage at the load connector. The microcontroller detects a drop of the load voltage to determine a moment when the load becomes connected to the circuit while the off command is being issued. The microcontroller issues the on command in response to the determination. Successive brief on commands may be issued to initially control current build-up in the load. A system includes the microcontroller and a plurality of such circuits for powering plural loads.

First claim

What is claimed is:

1. A circuit for powering a load, comprising:
a primary voltage source;
a load connector having a first port and a second port for connecting the load to the first and second ports, the second port being further connected to ground;
a primary transistor having a drain connected to the primary voltage source and a source connected to the first port of the load connector;
a secondary voltage source;
a top resistor having a first end connected to the secondary voltage source and a second end connected to a gate of the primary transistor;
a bottom resistor having a first end connected to the first port of the load connector and a second end connected to the ground;
a secondary transistor having a collector connected to the second end of the top resistor and an emitter connected to the first end of the bottom resistor;
a translator of commands operatively connected to a base of the secondary transistor, the translator of commands causing a closing of the secondary transistor and opening of the primary transistor when receiving an off command and causing an opening of the secondary transistor and closing of the primary transistor when receiving an on command;
a microcontroller adapted to:
initially issue the off command;
receive a measurement of a voltage at the first port of the load connector;
determine that the load is not connected to the load connector by detecting an intermediate voltage at the first port of the load connector while the off command is being issued;
determine that the load is connected to the load connector by detecting a low voltage at the first port of the load connector while the off command is being issued; and
issue the on command in response to the determination that the load is connected to the load connector.

2. The circuit of claim 1 , wherein the primary transistor is configured to be open when the low voltage or the intermediate voltage at the first port of the load connector is applied at its gate, and to be closed when a high voltage is applied at its gate.

3. The circuit of claim 1 , wherein the on command issued in response to the determination that the load is connected to the load connector is a first impulse command followed by an instance of the off command.

4. The circuit of claim 3 wherein the microcontroller is further adapted to:
issue a sequence of impulse commands for turning on the circuit, each impulse command being followed by a corresponding instance of the off command;
monitor the voltage at the load connector while issuing the sequence of impulse commands; and
terminate the sequence of impulse commands and issue a continuous on command when the voltage at the load connector reaches a nominal value.

5. The circuit of claim 1 , wherein:
closing the secondary transistor while the load is not connected to the load connector causes the application of the intermediate voltage at the gate of the primary transistor;
closing the secondary transistor while the load is connected to the load connector causes the application of the low voltage at the gate of the primary transistor; and
opening the secondary transistor causes the application of a high voltage at the gate of the primary transistor.

6. The circuit of claim 5 , wherein:
a primary voltage of the secondary voltage source is a constant DC voltage greater than a secondary, constant DC voltage of the primary voltage source; and
the high voltage applied at the gate of the primary transistor when the secondary transistor is opened is substantially equal to the secondary voltage of the secondary voltage source.

7. The circuit of claim 6 , further comprising:
an AC to DC converter adapted to supply the primary voltage of the primary voltage source; and
a DC to DC converter adapted to convert the primary voltage to the secondary voltage of the secondary voltage source.

8. The circuit of claim 6 , wherein the intermediate voltage is defined by the secondary voltage of the secondary voltage source and by the top and bottom resistors.

9. The circuit of claim 6 , wherein the low voltage is defined by the secondary voltage of the secondary voltage source, by the top resistor and by a parallel combination of the bottom resistor and of the load.

10. The circuit of claim 1 , wherein the secondary transistor is an optocoupler.

11. The circuit of claim 1 , wherein the primary transistor is a metal oxide semiconductor field effect transistor.

12. A system for powering multiple loads, comprising:
one or more channels, each channel being configured for powering a respective load, each channel comprising the circuit of claim 1 ;
wherein the microcontroller is operatively connected to the translator of commands of each of the one or more channels, the microcontroller being adapted to:
issue off and on commands to each channel independently,
receive measurements of voltages at the load connectors from each channel,
determine that no load is connected to the load connector of a given channel by detecting the intermediate voltage at the load connector of the given channel while the off command is being issued to the given channel,
determine that a load is connected to the load connector of the given channel by detecting the low voltage at the load connector of the given channel while the off command is being issued to the given channel, and
issue the on command to the translator of commands of the given channel in response to the determination that the load is connected to the load connector of the given channel.

13. The system of claim 12 , wherein the microcontroller is adapted to individually receive a measurement of a load voltage for each channel.

14. The system of claim 12 , wherein the microcontroller is adapted to individually receive a measurement of a load current for each channel.

15. The system of claim 14 , wherein the one or more channels comprise a plurality of channels, the system further comprising a demultiplexer adapted to individually transmit the off and on commands to the translator of commands of each channel.

16. The system of claim 15 , further comprising:
a first multiplexer adapted to individually receive the measurement of the load voltage from each of the plurality of channels; and
a second multiplexer adapted to individually receive the measurement of the load current from each of the plurality of channels.

Assignees

• OVH

Inventors

• Flipo Emmanuel Joseph Henri
• Thibaut Christophe Maurice

Classifications

• H02H3/087 Primary

  for DC applications · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02M1/0048

  Circuits or arrangements for reducing losses (using snubbers H02M1/34) · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• G05B19/0428

  Safety, monitoring (G05B19/0423 takes precedence) · CPC title