Multi-level inverter

Patent metadata

Field	Value
Publication number	US-10700588-B2
Application number	US-201916442214-A
Country	US
Kind code	B2
Filing date	Jun 14, 2019
Priority date	Mar 26, 2014
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

First claim

We claim:

1. An apparatus comprising:
first and second direct-current (DC) terminals;
a first circuit comprising a first plurality of switches that includes:
a) a first switch connected between the first DC terminal and a first node,
b) a second switch connected between a second node and a third node,
c) a third switch connected between the third node and a fourth node, and
d) a fourth switch connected between a fifth node and the second DC terminal;

a second circuit comprising a second plurality of switches that includes:
e) a fifth switch connected between the first DC terminal and the fourth node,
f) a sixth switch connected between the third node and the fifth node,
g) a seventh switch connected between the first node and the third node, and
h) an eighth switch connected between the second node and the second DC terminal;

a third circuit connected between the first node and the second node; and
a fourth circuit connected between the fourth node and the fifth node;
wherein:
the first plurality of switches and the second plurality of switches are configured to switch at a first frequency;
the apparatus is configured to output a first sine wave voltage from the third circuit and output a second sine wave voltage from the fourth circuit; and
the first sine wave voltage and the second sine wave voltage are each at the first frequency and 180 degrees phase shifted from each other.

2. The apparatus of claim 1 , wherein the third circuit and the fourth circuit each comprise one of a flying capacitor circuit, a half-bridge circuit, or a DC-to-DC converter.

3. The apparatus of claim 1 , wherein:
the third circuit comprises a first capacitor, connected between a sixth node and a seventh node, and a third plurality of switches including:
i) a ninth switch connected between the first node and the sixth node,
j) a tenth switch connected between the seventh node and the second node,
k) an eleventh switch connected between the sixth node and an eighth node, and
l) a twelfth switch connected between the seventh node and the eighth node; and

the fourth circuit comprises a second capacitor, connected between a ninth node and a tenth node, and a fourth plurality of switches including:
m) a thirteenth switch connected between the fourth node and the ninth node,
n) a fourteenth switch connected between the tenth node and the fifth node,
o) a fifteenth switch connected between the ninth node and an eleventh node, and
p) a sixteenth switch connected between the tenth node and the eleventh node.

4. The apparatus of claim 3 , wherein:
the third circuit comprises a third capacitor connected between the first and the second nodes; and
the fourth circuit comprises a fourth capacitor connected between the fourth and the fifth nodes.

5. The apparatus of claim 1 , wherein the first plurality of switches are configured to switch substantially complimentary to the second plurality of switches.

6. The apparatus of claim 5 , wherein the first plurality of switches are configured to switch substantially complimentary to the second plurality of switches such that the second and the third switches turn on and off with mutual dead time to turning on and off the sixth and the seventh switches.

7. The apparatus of claim 1 , wherein:
each switch of the first plurality of switches is configured to close during a first time period and open during a second time period, according to a first control signal; and
each switch of the second plurality of switches is configured to open during the first time period, and close during the second time period, according to a second control signal.

8. The apparatus of claim 1 , wherein the second and the third switches are configured to be open whenever the sixth switch or the seventh switch is closed, and the sixth and the seventh switches are configured to be open whenever the second switch or the third switch is closed.

9. The apparatus of claim 1 , wherein the first circuit is configured to conduct current through the second and the third switches, and the second circuit is configured to conduct current through the sixth and the seventh switches, such that ripple voltage is removed across the first and the second nodes, and removed across the fourth and the fifth nodes.

10. The apparatus of claim 9 , wherein:
the third and the fourth circuits are configured to operate at a second frequency that is greater than the first frequency; and
the first and the second circuits are configured to filter current at the second frequency from flowing between the second and the fourth nodes and from flowing between the fifth and the first nodes.

11. The apparatus of claim 1 , further comprising:
one or more first capacitors connected between the first DC terminal and the third node; and
one or more second capacitors connected between the second DC terminal and the third node.

12. The apparatus of claim 1 , wherein the apparatus is configured to:
switch, during a first half cycle of each of a plurality of cycles of the first sine wave voltage, the first plurality of switches on and the second plurality of switches off, and
switch, during a second half cycle of each of the plurality of cycles of the first sine wave voltage, the first plurality of switches off and the second plurality of switches on.

13. The apparatus of claim 1 , wherein:
the third circuit comprises a third plurality of switches, the fourth circuit comprises a fourth plurality of switches, and the third plurality of switches correspond, one-to-one, to the fourth plurality of switches; and
the apparatus further comprises a controller configured to switch the third plurality of switches and the fourth plurality of switches at a second frequency that is greater than the first frequency such that each switch of the third plurality of switches turns on and off in a complementary manner to its corresponding switch in the fourth plurality of switches.

14. The apparatus of claim 1 , wherein:
the third circuit comprises a third plurality of switches, and the fourth circuit comprises a fourth plurality of switches; and
the apparatus comprises a controller configured to switch the third plurality of switches and the fourth plurality of switches at a second frequency that is greater than the first frequency and that is greater than 16 kHz.

15. The apparatus of claim 14 , wherein the first frequency is 50 Hz or 60 Hz.

16. The apparatus of claim 1 , wherein:
the first circuit is configured to connect the third and the fourth circuits in series in a first order between the first and the second DC terminals; and
the second circuit is configured to connect the third and the fourth circuits in series in a second order between the first and the second DC terminals.

17. A method comprising:
controlling an apparatus to generate first and second sine wave voltages at a first frequency and 180 degrees phase shifted from each other;
wherein the apparatus comprises: first and second direct-current (DC) terminals, and first, second, third, and fourth circuits,
wherein the first circuit comprises a first plurality of switches that includes:
a) a first switch connected between the first DC terminal and a first node,
b) a second switch connected between a second node and a third node,
c) a third switch connected between the third node and a fourth node, and
d) a fourth switch connected between a fifth node and the second DC terminal,

wherein the second circuit comprises a second plurality of switches that includes:
e) a fifth switch connected between the first DC termin

Assignees

• Solaredge Technologies Ltd

Inventors

• Yoscovich Ilan
• Glovinsky Tzachi
• Sella Guy
• Galin Yoav

Classifications

• H02M7/483 Primary

  Converters with outputs that each can have more than two voltages levels · CPC title

• H02M7/4835

  comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage · CPC title

• H02M7/4837

  Flying capacitor converters · CPC title

• H02M7/4833

  Capacitor voltage balancing · CPC title

• H02M1/0095

  Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title