Systems and methods for fabrication of superconducting integrated circuits

Patent metadata

Field	Value
Publication number	US-10700256-B2
Application number	US-201715679963-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	Mar 8, 2012
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

First claim

The invention claimed is:

1. A superconducting integrated circuit comprising:
a first superconducting metal layer;
a first insulating barrier having a first thickness, wherein the first insulating barrier is positioned over the first superconducting metal layer;
a second superconducting metal layer positioned over the first insulating barrier;
a second insulating barrier having a second thickness, wherein the second insulating barrier is positioned over the second superconducting metal layer; and
a third superconducting metal layer positioned over the second insulating barrier;
a dielectric layer positioned over the third superconducting metal layer;
a superconducting wiring layer positioned over the dielectric layer; and
at least one superconducting via that superconductingly electrically couples at least a portion of the superconducting wiring layer to at least a portion of at least one of the second superconducting metal layer and the third superconducting metal layer.

2. The superconducting integrated circuit of claim 1 wherein the second thickness of the second insulating barrier is greater than the first thickness of the first insulating barrier.

3. The superconducting integrated circuit of claim 1 wherein at least a first portion of the superconducting integrated circuit is patterned to form a first Josephson junction comprising:
a first portion of the third superconducting metal layer;
a first portion of the second insulating barrier;
a first portion of the second superconducting metal layer;
a first portion of the first insulating barrier; and
a first portion of the first superconducting metal layer,
and wherein at least one superconducting via superconductingly electrically couples a first portion of the superconducting wiring layer to the first portion of the third superconducting metal layer.

4. The superconducting integrated circuit of claim 3 wherein at least a second portion of the superconducting integrated circuit is patterned to form a second Josephson junction comprising:
a second portion of the second superconducting metal layer;
a second portion of the first insulating barrier; and
a second portion of the first superconducting metal layer,
and wherein at least one superconducting via superconductingly electrically couples a second portion of the superconducting wiring layer to the second portion of the second superconducting metal layer.

5. The superconducting integrated circuit of claim 1 wherein at least a first portion of the superconducting integrated circuit is patterned to form a first Josephson junction comprising:
a first portion of the second superconducting metal layer;
a first portion of the first insulating barrier; and
a first portion of the first superconducting metal layer,
and wherein at least one superconducting via superconductingly electrically couples a first portion of the superconducting wiring layer to the first portion of the second superconducting metal layer.

6. The method of claim 1 wherein the first insulating barrier comprises:
a first layer of silicon nitride that directly overlies the first superconducting metal layer;
a layer of silicon dioxide that directly overlies the first layer of silicon nitride; and
a second layer of silicon nitride that directly overlies the layer of silicon dioxide.

7. The superconducting integrated circuit of claim 5 wherein at least a second portion of the superconducting integrated circuit is patterned to form a second Josephson junction comprising:
a first portion of the third superconducting metal layer;
a first portion of the second insulating barrier; and
a second portion of the second superconducting metal layer,
and wherein at least one superconducting via superconductingly electrically couples a second portion of the superconducting wiring layer to the first portion of the third superconducting metal layer.

8. The superconducting integrated circuit of claim 7 wherein the first Josephson junction has a first critical current density, the second Josephson junction has a second critical current density, and the first thickness of the first insulating layer and the second thickness of the second insulated layer are selected such that the first critical current density of the first Josephson junction is less than the second critical current density of the second Josephson junction.

9. The superconducting integrated circuit of claim 4 wherein the first Josephson junction has a first critical current density, the second Josephson junction has a second critical current density, and the first thickness of the first insulating layer and the second thickness of the second insulated layer are selected such that the first critical current density of the first Josephson junction is less than the second critical current density of the second Josephson junction.

Assignees

• D Wave Systems Inc

Inventors

• Ladizinsky Eric
• Hilton Jeremy P
• Oh Byong Hyop
• Bunyk Paul I

Classifications

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title