MOSFET and power conversion circuit

Patent metadata

Field	Value
Publication number	US-10700191-B2
Application number	US-201616331138-A
Country	US
Kind code	B2
Filing date	Sep 16, 2016
Priority date	Sep 16, 2016
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A MOSFET used in a power conversion circuit including a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure, the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.

First claim

The invention claimed is:

1. A MOSFET used in a power conversion circuit which includes at least: a reactor; a power source which supplies an electric current to the reactor; the MOSFET for controlling an electric current supplied from the power source to the reactor; and a rectifier element which performs a rectifying operation of the electric current supplied from the power source to the reactor or an electric current from the reactor, wherein
the MOSFET comprises a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure,
the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and
the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.

2. The MOSFET according to claim 1 , wherein the total amount of the dopant in the p-type column region is set in a range of 1.05 times to 1.15 times as much as the total amount of the dopant in the n-type column region.

3. The MOSFET according to claim 1 , wherein the semiconductor base substrate further includes: a p-type base region formed on a surface of a portion of the n-type column region and a whole surface of the p-type column region; and an n-type source region formed on a surface of the base region, and
the MOSFET is a planar-gate-type MOSFET which further includes a gate electrode formed on the base region sandwiched between the source region and the n-type column region by way of a gate insulation film.

4. The MOSFET according to claim 3 , wherein the semiconductor base substrate further includes an n-type surface high concentration diffusion region formed on a portion of the surface of the n-type column region where the base region is not formed.

5. The MOSFET according to claim 1 , wherein the semiconductor base substrate further includes: a p-type base region formed on a surface of the n-type column region and a surface of the p-type column region; and an n-type source region formed on a surface of the base region, and
the MOSFET is a trench-gate-type MOSFET which further includes: a trench where the trench is formed so as to reach a depth position deeper than a deepest portion of the base region in a region where the n-type column region is positioned as viewed in a plan view, and a portion of the source region is exposed on an inner peripheral surface of the trench; and a gate electrode embedded in the inside of the trench by way of a gate insulation film formed on the inner peripheral surface of the trench.

6. The MOSFET according to claim 5 , wherein the semiconductor base substrate has an n-type high concentration dopant region which is formed in a region deeper than a bottommost portion of the base region and shallower than a bottommost portion of the trench.

7. The MOSFET according to claim 1 , wherein the p-type column region has the structure where a width of the p-type column region is gradually increased as the p-type column region extends from a deep portion of the p-type column region toward a surface of the p-type column region.

8. The MOSFET according to claim 1 , wherein the p-type column region has the structure where dopant concentration in the p-type column region is gradually increased as the p-type column region extends from a deep portion of the p-type column region toward a surface of the p-type column region.

9. A power conversion circuit comprising at least:
a reactor;
a power source which supplies an electric current to the reactor;
the MOSFET according to claim 1 for controlling an electric current supplied from the power source to the reactor; and
a rectifier element which performs a rectifying operation of the electric current supplied from the power source to the reactor or an electric current from the reactor.

10. The power conversion circuit according to claim 9 , wherein the rectifier element is a fast recovery diode.

11. The power conversion circuit according to claim 9 , wherein the rectifier element is a built-in diode of the MOSFET.

12. The power conversion circuit according to claim 9 , wherein the rectifier element is a silicon-carbide Schottky barrier diode.

Assignees

• Shindengen Electric Mfg

Inventors

• Arai Daisuke
• Hisada Shigeru
• Kitada Mizue
• Asada Takeshi

Classifications

• H10D30/662

  having a drift region having a doping concentration that is higher between adjacent body regions relative to other parts of the drift region · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D48/32

  Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched · CPC title