Silicon-controlled rectifier structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10700186-B2
Application number	US-201816192818-A
Country	US
Kind code	B2
Filing date	Nov 16, 2018
Priority date	Aug 20, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, wherein an N-type heavily-doped region 410 and a P-type heavily-doped region 422 which are connected to an anode are provided in the N-Well, and a floating guard ring 416 is further provided in the N-Well between the N-type heavily-doped region 410 and the P-type heavily-doped region 422, the guard ring being spaced from the N-type heavily-doped region 410 by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region 422; and an N-type heavily-doped region 414 and a P-type heavily-doped region 424 which are connected to a cathode are provided in the P-Well.

First claim

What is claimed is:

1. A silicon-controlled rectifier structure, comprising:
a substrate; and
an N-Well and a P-Well in the substrate, the N-Well abutting the P-Well, wherein
an N-type heavily-doped region and a P-type heavily-doped region which are connected to an anode are provided in the N-Well, the N-type heavily-doped region spans the N-Well and the P-Well, and a floating guard ring is further provided in the N-Well between the N-type heavily-doped region and the P-type heavily-doped region, the floating guard ring being spaced from the N-type heavily-doped region by a shallow trench isolation, and an active area having a predetermined width exists between the floating guard ring and the P-type heavily-doped region; and
an N-type heavily-doped region and a P-type heavily-doped region which are connected to a cathode are provided in the P-Well, the N-type heavily-doped region being spaced from P-type heavily-doped region by a shallow trench isolation, and a gated diode connected to the cathode being provided between the N-type heavily-doped region and the N-type heavily-doped region;
wherein a P-type doped, ESD heavily-doped region is further provided in the P-Well under the N-type heavily-doped region and abutting the N-Well.

2. The silicon-controlled rectifier structure of claim 1 , wherein the floating guard ring is an N-type heavily-doped region.

3. The silicon-controlled rectifier structure of claim 2 , wherein the concentration of heavily-doped ions in the floating guard ring ranges from 1E14 cm −2 to 1E16 cm −2 .

4. The silicon-controlled rectifier structure of claim 1 , wherein the width of the floating guard ring ranges from 0.1 um to 10 um.

5. The silicon-controlled rectifier structure of claim 1 , wherein the predetermined width of the active area ranges from 0.2 um to 10 um.

6. A manufacturing method for a silicon-controlled rectifier structure, comprising:
providing a substrate;
forming an N-Well and a P-Well in the substrate, the N-Well abutting the P-Well;
forming an N-type heavily-doped region spans the N-Well and the P-Well at a position where the N-Well abuts the P-Well;
forming a P-type heavily-doped region in the N-Well;
forming a guard ring between the N-type heavily-doped region and the P-type heavily-doped region;
forming an N-type heavily-doped region and a P-type heavily-doped region in the P-Well;
forming a P-type doped, ESD heavily-doped region in the P-Well under the N-type heavily-doped region and abutting the N-Well;
forming a shallow trench isolation between the guard ring and the N-type heavily-doped region, an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region;
forming a shallow trench isolation between the N-type heavily-doped region and the P-type heavily-doped region;
forming a gated diode between the N-type heavily-doped region and the N-type heavily-doped region; and
connecting the N-type heavily-doped region and the P-type heavily-doped region to the anode, floating the guard ring and connecting the N-type heavily-doped region, the P-type heavily-doped region, and a gate of the gated diode to the cathode.

7. The manufacturing method of claim 6 , wherein the step of forming the guard ring further comprises: performing N-type ion heavy doping between the N-type heavily-doped region and the P-type heavily-doped region, the concentration of the N-type ion heavy doping ranging from 1E14 cm −2 to 1E16 cm −2 .

8. The manufacturing method of claim 6 , further comprising:
forming a shallow trench isolation abutting the P-type heavily-doped region on a side of the N-Well opposite to a side abutting the P-Well; and
forming a shallow trench isolation abutting the P-type heavily-doped region on a side of the P-Well opposite to a side abutting the N-Well.

9. The manufacturing method of claim 6 , comprising forming the guard ring having the width ranging from 0.1 um to 10 um.

10. The manufacturing method of claim 6 , comprising forming the guard ring within the N-Well at a distance of 0.2 um to 10 um from the P-type heavily-doped region.

Assignees

• Shanghai Huali Microelect Corp

Inventors

• Zhu Tianzhi

Classifications

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D18/01

  Manufacture or treatment · CPC title

• H10D8/041

  of multilayer diodes · CPC title

• H10D64/111

  Field plates · CPC title