Array substrate and method for manufacturing the same, display panel and display device

Patent metadata

Field	Value
Publication number	US-10700105-B2
Application number	US-201816131959-A
Country	US
Kind code	B2
Filing date	Sep 14, 2018
Priority date	Nov 28, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

An array substrate, a method for manufacturing an array substrate, a display panel and a display device are provided. The array substrate includes: a base substrate including a display area and a non-display area; a dummy data line in the non-display area of the base substrate; and an effective data line in the non-display area of the base substrate. The dummy data line is closer to an edge of the base substrate than the effective data line, and a width of the dummy data line is greater than a width of the effective data line.

First claim

What is claimed is:

1. An array substrate comprising:
a base substrate comprising a display area and a non-display area;
a dummy data line in the non-display area of the base substrate; and
an effective data line in the non-display area of the base substrate,
wherein the dummy data line is closer to an edge of the base substrate than the effective data line, and a width of the dummy data line is greater than a width of the effective data line,
wherein the effective data line extends in a first direction, the dummy data line is spaced apart from the effective data line in a second direction, and the first direction is perpendicular to the second direction, and
wherein the dummy data line comprises a plurality of metal lines intersecting with each other, a first part of the metal lines extend in a third direction, a second part of the metal lines extend in a fourth direction, the third direction intersects with the fourth direction, and both the third direction and the fourth direction intersect with each of the first direction and the second direction.

2. The array substrate according to claim 1 , wherein a difference between the width of the dummy data line and the width of the effective data line is greater than 0.5 μm and less than or equal to 68 μm.

3. The array substrate according to claim 1 , wherein the width of the dummy data line is greater than 2.5 μm and less than or equal to 70 μm.

4. The array substrate according to claim 3 , wherein the width of the dummy data line is greater than 10 μm and less than or equal to 20 μm.

5. The array substrate according to claim 1 , wherein a width of each of the metal lines is equal to or greater than the width of the effective data line.

6. The array substrate according to claim 1 , wherein at least one of a material of the dummy data line and a material of the effective data line is selected from at least one of Mo, Al, Ti, Au, Cu, Hf and Ta.

7. The array substrate of claim 1 , further comprising: a planarization layer disposed over the dummy data line and the effective data line.

8. A display panel comprising the array substrate according to claim 1 .

9. A display device comprising the display panel according to claim 8 .

10. A method for manufacturing an array substrate, comprising:
providing a base substrate comprising a display area and a non-display area; and
forming a dummy data line and an effective data line in the non-display area of the base substrate,
wherein the dummy data line is closer to an edge of the base substrate than the effective data line, and a width of the dummy data line is greater than a width of the effective data line,
wherein the effective data line extends in a first direction, the dummy data line is spaced apart from the effective data line in a second direction, and the first direction is perpendicular to the second direction, and
wherein the dummy data line comprises a plurality of metal lines intersecting with each other, a first part of the metal lines extend in a third direction, a second part of the metal lines extend in a fourth direction, the third direction intersects with the fourth direction, and both the third direction and the fourth direction intersect with each of the first direction and the second direction.

11. The method according to claim 10 , wherein forming the dummy data line and the effective data line in the non-display area of the base substrate comprises:
forming the dummy data line and the effective data line in the non-display area of the base substrate through one patterning process.

12. The method according to claim 11 , wherein forming the dummy data line and the effective data line in the non-display area of the base substrate through one patterning process comprises:
forming a conductive material layer on the base substrate;
forming a photoresist layer on the conductive material layer;
exposing the photoresist layer by using a mask;
developing the exposed photoresist layer; and
etching the conductive material layer through a dry etching process to form the dummy data line and the effective data line.

13. The method according to claim 12 , wherein the mask comprises a first portion for forming the dummy data line and a second portion for forming the effective data line, and a width of the first portion is greater than a width of the second portion.

14. The method according to claim 13 , wherein the first portion comprises a plurality of first sub-portions, the plurality of first sub-portions intersecting with each other to form a grid.

15. The method according to claim 10 , wherein a difference between the width of the dummy data line and the width of the effective data line is greater than 0.5 μm and less than or equal to 68 μm.

16. The method according to claim 10 , wherein the width of the dummy data line is greater than 2.5 μm and less than or equal to 70 μm.

17. The method according to claim 16 , wherein the width of the dummy data line is greater than 10 μm and less than or equal to 20 μm.

18. The method according to claim 10 , further comprising: forming a planarization layer over the dummy data line and the effective data line.

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Li Yanfeng
• Yu Yanan
• Xu Jingyi
• Zhao Xin
• Wang Xiaokang
• Ren Yanwei
• Li Wei

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F1/133

  Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title