Thin film transistor array substrate, display apparatus, and method of manufacturing thin film transistor array substrate

Patent metadata

Field	Value
Publication number	US-10700104-B2
Application number	US-201816047248-A
Country	US
Kind code	B2
Filing date	Jul 27, 2018
Priority date	Aug 8, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A thin film transistor array substrate includes: a first conductive layer including first lines for transmitting data signals to the thin film transistors; a second conductive layer disposed on the first conductive layer and including second lines for supplying a driving voltage to the thin film transistors; a first insulating layer disposed between a semiconductor layer and the first conductive layer and including a first material layer; a second insulating layer disposed between the first conductive layer and the second conductive layer and including a second material layer having a dielectric constant greater than that of the first material layer; and a contact plug penetrating the second insulating layer and the first insulating layer, and connecting the second conductive layer to the semiconductor layer. A taper angle of the contact plug in the second material layer is greater than that of the contact plug in the first material layer.

First claim

What is claimed is:

1. A thin film transistor array substrate comprising:
a substrate;
a semiconductor layer disposed on the substrate and comprising active areas of a plurality of thin film transistors;
a first conductive layer disposed on the semiconductor layer and comprising a plurality of first lines for transmitting data signals to the plurality of thin film transistors;
a second conductive layer disposed on the first conductive layer and comprising a plurality of second lines for supplying a driving voltage to the plurality of thin film transistors;
a first insulating layer disposed between the semiconductor layer and the first conductive layer and comprising a first material layer having a first dielectric constant;
a second insulating layer disposed between the first conductive layer and the second conductive layer and comprising a second material layer having a second dielectric constant that is greater than the first dielectric constant; and
a contact plug penetrating the second insulating layer and the first insulating layer and connecting the second conductive layer to the semiconductor layer,
wherein a second taper angle of the contact plug in the second material layer is greater than a first taper angle of the contact plug in the first material layer.

2. The thin film transistor array substrate of claim 1 , further comprising a first capacitor that comprises a portion of the first conductive layer as a lower electrode and a portion of the second conductive layer as an upper electrode.

3. The thin film transistor array substrate of claim 1 , wherein the second material layer comprises at least one of zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), tantalum pentoxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), strontium titanate (SrTiO 3 ), and barium titanate (BaTiO 3 ).

4. The thin film transistor array substrate of claim 1 , wherein the second conductive layer comprises source electrodes and drain electrodes of the plurality of thin film transistors.

5. The thin film transistor array substrate of claim 1 , further comprising a first gate layer and a second gate layer between the semiconductor layer and the first insulating layer,
wherein the first gate layer comprises gate electrodes of the plurality of thin film transistors, and
the second gate layer is on the first gate layer and comprises a plurality of third lines for transmitting a scan signal and a control signal to the plurality of thin film transistors.

6. The thin film transistor array substrate of claim 5 , further comprising a second capacitor that comprises one gate electrode of the first gate layer as a lower electrode and a portion of the second gate layer as an upper electrode.

7. The thin film transistor array substrate of claim 5 , further comprising a third insulating layer disposed between the first gate layer and the second gate layer and comprising a third material layer having a third dielectric constant.

8. The thin film transistor array substrate of claim 7 , wherein the third dielectric constant is greater than the first dielectric constant, and
a third taper angle of the contact plug in the third material layer is greater than the first taper angle of the contact plug in the first material layer.

9. The thin film transistor array substrate of claim 8 , wherein the third material layer comprises at least one of ZrO 2 , TiO 2 , Ta 2 O 5 , Al 2 O 3 , SrTiO 3 , and BaTiO 3 .

10. A display apparatus comprising:
a substrate;
a thin film transistor disposed on the substrate, configured to drive pixels, and comprising an active area, a gate electrode, a source electrode, and a drain electrode;
a first capacitor comprising a second conductive pattern as an upper electrode and a first conductive pattern as a lower electrode, wherein the second conductive pattern is on a layer the same as that of the source electrode and the drain electrode, and the first conductive pattern overlaps at least a portion of the second conductive pattern;
a first insulating layer disposed between the gate electrode and the first conductive pattern and comprising a first material layer having a first dielectric constant;
a second insulating layer disposed between the first conductive pattern and the second conductive pattern and comprising a second material layer having a second dielectric constant; and
a contact plug penetrating the second insulating layer and the first insulating layer and connecting the second conductive pattern to the active area,
wherein a second taper angle of the contact plug in the second material layer is greater than a first taper angle of the contact plug in the first material layer.

11. The display apparatus of claim 10 , further comprising a second capacitor that comprises the gate electrode as a lower electrode, and a third conductive pattern as an upper electrode,
wherein the third conductive pattern is on a layer between the gate electrode and the first insulating layer, and at least a portion of the third conductive pattern overlaps the gate electrode.

12. The display apparatus of claim 11 , further comprising a third insulating layer disposed between the gate electrode and the third conductive pattern and comprising a third material layer having a third dielectric constant.

13. The display apparatus of claim 12 , wherein the third dielectric constant is greater than the first dielectric constant, and
a third taper angle of the contact plug in the third material layer is greater than the first taper angle of the contact plug in the first material layer.

14. A thin film transistor array substrate comprising:
a substrate;
a semiconductor layer disposed on the substrate and comprising active areas of thin film transistors;
a first conductive layer disposed on the semiconductor layer and comprising first lines for transmitting data signals to the thin film transistors;
a second conductive layer disposed on the first conductive layer and comprising second lines for supplying a driving voltage to the thin film transistors;
a first insulating layer disposed between the semiconductor layer and the first conductive layer and comprising a first material layer;
a second insulating layer disposed between the first conductive layer and the second conductive layer and comprising a second material layer; and
a contact plug penetrating the second insulating layer and the first insulating layer and connecting the second conductive layer to the semiconductor layer,
wherein a second taper angle of the contact plug in the second material layer is greater than a first taper angle of the contact plug in the first material layer, and
the second material layer has a dielectric constant greater than that of silicon oxide (SiO 2 ) or silicon nitride (SiNO n ).

15. The thin film transistor array substrate of claim 14 , further comprising a capacitor that comprises a portion of the first conductive layer as a lower electrode and a portion of the second conductive layer as an upper electrode.

16. The thin film transistor array substrate of claim 14 , wherein the second material layer comprises one or more of hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO x ), hafnium aluminum oxide (HfAlO x ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAlO 3 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 4 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), barium strontium titanium oxide (BaSrTi 2 O 6 ), barium titanium oxide (BaTiO 3 ), strontium titanium oxide (SrTiO 3 ), yttrium oxide (Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), lead scandium tantalum oxide (Pb(Sc,Ta)O 3 ), and lea

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Jinwoo
• Kim Waljun
• Ahn Kiwan
• Jang Yongjae
• Jang Jaehyuk
• Jeong Yugwang

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/431

  having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs · CPC title

• H10D86/411 Primary

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title