Static random access memory (SRAM) cell and related SRAM array for deep neural network and machine learning applications

Patent metadata

Field	Value
Publication number	US-10699778-B2
Application number	US-201815961220-A
Country	US
Kind code	B2
Filing date	Apr 24, 2018
Priority date	Apr 28, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A static random access memory (SRAM) bit cell and a related SRAM array are provided. In one aspect, an SRAM cell is configured to perform an XNOR function on a first input value and a second input value. In another aspect, a number of the SRAM cells can be employed to form an SRAM array for supporting deep neural network and machine learning applications. The SRAM cell is coupled to a word line(s) and an inverted word line(s) that collectively define the first input value. The SRAM cell causes a voltage and/or current difference between a bit line(s) and a complementary bit line(s) coupled to the SRAM cell. By customizing the SRAM cell to enable the XNOR function and forming a binary neural network based on the SRAM array, it is possible to effectively implement computing-in-memory (CIM) for deep neural network and machine learning applications.

First claim

What is claimed is:

1. A static random access memory (SRAM) cell comprising:
at least one word line input coupled to at least one word line;
at least one inverted word line input coupled to at least one inverted word line;
at least one bit line input coupled to at least one bit line;
at least one complementary bit line input coupled to at least one complementary bit line; and
at least one SRAM bit cell configured to:
receive a first input value collectively defined by the at least one word line and the at least one inverted word line;
perform an XNOR function based on the first input value and a second input value pre-stored in the at least one SRAM bit cell; and
cause a voltage difference between the at least one bit line and the at least one complementary bit line, wherein the voltage difference corresponds to a binary output of the XNOR function, wherein:
the voltage difference is less than zero when the first input value is different from the second input value; and
the voltage difference is greater than zero when the first input value is the same as the second input value.

2. The SRAM cell of claim 1 wherein the binary output of the XNOR function equals minus one (−1) when the voltage difference is less than zero and plus one (+1) when the voltage difference is greater than zero.

3. The SRAM cell of claim 1 wherein the first input value and the second input value represent a binarized neuron activation and a binarized synaptic weight of a deep neural network, respectively.

4. The SRAM cell of claim 1 wherein the at least one SRAM bit cell is further configured to cause a current difference between the at least one bit line and the at least one complementary bit line, wherein the current difference corresponds to the binary output of the XNOR function.

5. The SRAM cell of claim 4 wherein:
the current difference is less than zero when the first input value is different from the second input value; and
the current difference is greater than zero when the first input value is the same as the second input value.

6. The SRAM cell of claim 5 wherein the binary output of the XNOR function equals minus one (−1) when the current difference is less than zero and plus one (+1) when the current difference is greater than zero.

7. The SRAM cell of claim 1 wherein:
the at least one word line and the at least one inverted word line collectively define a positive binarized neuron activation when the at least one word line and the at least one inverted word line are activated and deactivated, respectively; and
the at least one word line and the at least one inverted word line collectively define a negative binarized neuron activation when the at least one word line and the at least one inverted word line are deactivated and activated, respectively.

8. The SRAM cell of claim 1 wherein the at least one SRAM bit cell comprises:
a first six-transistor (6T) SRAM bit cell coupled to the at least one word line and comprising:
a first storing node coupled to the at least one bit line via a first pass gate; and
a first inverted storing node coupled to the at least one complementary bit line via a second pass gate; and

a second 6T SRAM bit cell coupled to the at least one inverted word line and comprising:
a second storing node coupled to the at least one complementary bit line via a third pass gate; and
a second inverted storing node coupled to the at least one bit line via a fourth pass gate.

9. The SRAM cell of claim 1 wherein the at least one SRAM bit cell comprises an eight-transistor (8T) SRAM bit cell, the 8T SRAM bit cell comprising:
a storing node coupled to the at least one bit line and the at least one word line via a first pass gate;
the storing node further coupled to the at least one inverted word line and the at least one complementary bit line via a second pass gate;
an inverted storing node coupled to the at least one word line and the at least one complementary bit line via a third pass gate; and
the inverted storing node further coupled to the at least one inverted word line and the at least one bit line via a fourth pass gate.

10. The SRAM cell of claim 1 wherein:
the at least one word line comprises a first word line and a second word line;
the at least one inverted word line comprises an inverted word line; and
the at least one SRAM bit cell comprises a seven-transistor (7T) SRAM bit cell, the 7T SRAM bit cell comprising:
a storing node coupled to the at least one bit line and the second word line via a first pass gate;
an inverted storing node coupled to the first word line and the at least one complementary bit line via a third pass gate; and

the inverted storing node further coupled to the inverted word line and the at least one bit line via a fourth pass gate.

11. The SRAM cell of claim 1 wherein:
the at least one word line comprises a read word line;
the at least one inverted word line comprises an inverted read word line;
the at least one bit line comprises a read bit line;
the at least one complementary bit line comprises a complementary read bit line; and
the at least one SRAM bit cell comprises a ten-transistor (10T) SRAM bit cell, the 10T SRAM bit cell comprising:
a storing node coupled to the read word line and the read bit line via a first pass gate and a second pass gate; and
an inverted storing node coupled to the inverted read word line and the complementary read bit line via a third pass gate and a fourth pass gate.

12. The SRAM cell of claim 11 wherein:
the storing node is further coupled to a write word line and a write bit line via a fifth pass gate; and
the inverted storing node is further coupled to the write word line and a complementary write bit line via a sixth pass gate;
wherein the write word line, the write bit line, and the complementary write bit line are configured to enable writing the second input value into the 10T SRAM bit cell.

Assignees

• Yu Shimeng
• Liu Rui
• Univ Arizona State

Inventors

• Yu Shimeng
• Liu Rui

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• H10B10/12

  comprising a MOSFET load element · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title