In situ transposition

Patent metadata

Field	Value
Publication number	US-10698975-B2
Application number	US-201616063793-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Jan 27, 2016
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.

First claim

What is claimed is:

1. A system, comprising:
a non-volatile memory (NVM) array, comprising a plurality of NVM elements, usable in performance of computations;
an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements; and
a transposition engine to direct performance of in situ transposition such that the plurality of data values remains stored by the original NVM elements wherein:
the transposition engine directs selectable coupling of a digital to analog converter (DAC) resource and an analog to digital converter (ADC) resource; and
the selectable coupling performs the in situ transposition by a row of NVM elements operating as a column and a column of NVM elements operating as a row.

2. The system of claim 1 , wherein:
the input engine inputs the plurality of data values for storage at original positions of a two dimensional matrix of the corresponding plurality of the original NVM elements; and
the transposition engine directs performance of the in situ transposition such that the plurality of data values remains stored at the original positions.

3. The system of claim 1 , wherein at least one NVM element is a resistive memory element.

4. The system of claim 1 , wherein the NVM array is a dot product engine (DPE) to store the input plurality of data values as a matrix.

5. The system of claim 1 , wherein the system further comprises:
a truncate engine to send a truncate signal; and
a truncate transistor associated with a row select wire at a particular location to disable, based on receipt of the truncate signal, a row signaling path at the particular location; and
wherein to disable the row signaling path at the particular location isolates a column of NVM elements intersected by a row of NVM elements to reduce activation of NVM elements to a subset of columns of the NVM array.

6. A non-transitory machine-readable medium storing instructions executable by a processing resource to:
input a plurality of data values for storage at original positions of a two dimensional matrix of a corresponding plurality of non-volatile memory (NVM) elements of an NVM array;
selectably couple, via a first DAC/ADC multiplexer, row wires of the NVM array to one of a digital to analog converter (DAC) resource and an analog to digital converter (ADC) resource;
selectably couple, via a second DAC/ADC multiplexer, column wires of the NVM array to the other one of the DAC resource and the ADC resource; and
perform in situ transposition of the plurality of data values by the selectably coupled DAC and ADC resources enabling rows of the NVM elements to operate as columns and columns of NVM elements to operate as rows; and
wherein the plurality of data values remains stored at the original positions of the two dimensional matrix.

7. The medium of claim 6 , the instructions further executable to:
decouple, via the first DAC/ADC multiplexer, a coupled DAC resource from a row wire and couple the ADC resource to the row wire for the in situ transposition; and
decouple, via the second DAC/ADC multiplexer, a coupled ADC resource from a column wire and couple the DAC resource to the column wire for the in situ transposition.

8. A method, comprising:
operating a non-volatile memory (NVM) array, comprising a plurality of NVM elements, as a plurality of dot product engines (DPEs);
storing, as a matrix, a plurality of data values by a corresponding plurality of original NVM elements;
performing in situ transposition of the plurality of data values such that the plurality of data values remains stored by the original NVM elements;
inputting a multibit input vector to the plurality of DPEs as one bit per DPE; and
wherein the plurality of DPEs corresponds to the number of bits in the multibit input vector.

9. The method of claim 8 , further comprising:
performing vector-matrix multiplication between the multibit input vector and the plurality of transposed data values stored as the matrix by the original NVM elements.

10. A system, comprising:
a non-volatile memory (NVM) array, comprising a plurality of NVM elements, usable in performance of computations;
an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements;
a transposition engine to direct performance of in situ transposition such that the plurality of data values remains stored by the original NVM elements
a digital to analog converter (DAC) resource;
an analog to digital converter (ADC) resource;
a first DAC/ADC multiplexer to selectably couple row wires of the NVM array to one of the DAC resource and the ADC resource; and
a second DAC/ADC multiplexer to selectably couple column wires of the NVM array to the other one of the DAC resource and the ADC resource.

11. The system of claim 10 , wherein at least one NVM element is a resistive memory element.

12. The system of claim 10 , wherein the NVM array is a dot product engine (DPE) to store the input plurality of data values as a matrix.

13. The system of claim 10 , wherein:
the first DAC/ADC multiplexer is selectably coupled to the row wires of the NVM array via a first data multiplexer; and
the second DAC/ADC multiplexer is selectably coupled to the column wires of the NVM array via a second data multiplexer.

14. The system of claim 10 , wherein:
the DAC resource comprises a plurality of DACs that corresponds to a plurality of physical rows or columns in the NVM array; and
the ADC resource comprises at least one ADC that is time multiplexable by a subset of the plurality of physical rows and columns in the NVM array such that a number of ADCs is less than the plurality of physical rows or columns.

15. A method, comprising:
operating a non-volatile memory (NVM) array, comprising a plurality of NVM elements, as a plurality of dot product engines (DPEs);
storing, as a matrix, a plurality of data values by a corresponding plurality of original NVM elements;
performing in situ transposition of the plurality of data values such that the plurality of data values remains stored by the original NVM elements;
inputting a multibit input vector to a row wire of the DPE via a digital to analog converter (DAC) resource having a corresponding multibit DAC selectably coupled to the row wire; and
inputting a single bit input vector directly to the row wire of the DPE without using the DAC resource.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Muralimanohar Naveen
• Feinberg Benjamin
• Strachan John Paul

Classifications

• G06G7/16 Primary

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title