Alternative protocol selection

Patent metadata

Field	Value
Publication number	US-10698856-B1
Application number	US-201816223873-A
Country	US
Kind code	B1
Filing date	Dec 18, 2018
Priority date	Dec 18, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.

First claim

What is claimed is:

1. A link controller comprising:
a physical layer circuit adapted to be coupled to a communication link and provide a data lane over said communication link;
a first data link layer controller which operates according to a first Peripheral Component Interconnect Express (PCIe) protocol;
a second data link layer controller which operates according to a second non-PCIe protocol;
a multiplexer/demultiplexer coupled to the first data link layer controller, the second data link layer controller, and the physical layer circuit;
a link training and status state machine (LTSSM) which selectively controls the physical layer circuit to:
transmit and receive training ordered sets over the data lane;
inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane;
transmit and receive data rate information and link width information over the data lane; and
in response to receiving the alternative protocol negotiation information, cause the multiplexer/demultiplexer to selectively couple the physical layer circuit to the second data link layer controller.

2. The link controller of claim 1 , wherein the second protocol is a Gen-Z protocol.

3. The link controller of claim 2 , wherein:
the alternative protocol negotiation information is included in modified training ordered sets.

4. The link controller of claim 3 , wherein the LTSSM further selectively controls the physical layer circuit to:
in response to receiving unmodified training ordered sets, cause the multiplexer/demultiplexer to selectively couple the physical layer circuit to the first data link layer controller.

5. The link controller of claim 2 , further comprising:
a Gen-Z transaction layer controller coupled to the second data link layer controller; and
a PCIe transaction layer controller coupled to the first data link layer controller.

6. The link controller of claim 1 , wherein the LTSSM transmits and receives the alternative protocol negotiation information based on status of a control register.

7. A method comprising:
transmitting and receiving modified training ordered sets using a link controller circuit adapted to be coupled to a Peripheral Component Interconnect Express (PCIe) communication link;
inside the modified training ordered sets, transmitting and receiving alternative protocol negotiation information over a data lane;
transmitting and receiving data rate information and link width information using the link controller circuit;
in response to not receiving the alternative protocol negotiation information, selectively causing a multiplexer/demultiplexer to connect a physical layer circuit to a first Peripheral Component Interconnect Express (PCIe) data link layer controller for a first protocol;
in response to receiving the alternative protocol negotiation information, selectively causing the multiplexer/demultiplexer to selectively couple the physical layer circuit to a second non-PCIe data link layer controller for a second protocol; and
subsequently operating the PCIe communication link.

8. The method of claim 7 , wherein the second protocol is a Gen-Z protocol.

9. The method of claim 7 , further comprising, after selectively causing the multiplexer/demultiplexer to selectively couple the physical layer circuit to the second data link layer controller for the second protocol, operating the communication link with a Gen-Z protocol.

10. The method of claim 7 , wherein transmitting and receiving alternative protocol negotiation information is performed through the physical layer circuit under control of a link training and status state machine (LTSSM).

11. The method of claim 7 , wherein transmitting and receiving alternative protocol negotiation information is done based on a predetermined status of a control register.

12. A data processing platform comprising:
a central processing unit;
a dual-protocol link controller coupled to said central processing unit and comprising:
physical layer circuit coupled to a Peripheral Component Interconnect Express (PCIe) communication link;
a first data link layer controller adapted to operate according to a first Peripheral Component Interconnect Express (PCIe) protocol;
a second data link layer controller adapted to operate according to a second non-PCIe protocol;
a multiplexer/demultiplexer coupled to the first data link layer controller, the second data link layer controller, and the physical layer circuit;
a link training and status state machine (LTSSM) adapted to control the physical layer circuit to: (a) transmit and receive training ordered sets over the PCIe communication link; (b) inside the training ordered sets, transmit and receive alternative protocol negotiation information over the PCIe communication link; and (c) in response to receiving the alternative protocol negotiation information, cause the multiplexer/demultiplexer to connect the physical layer circuit to the second data link layer controller.

13. The data processing platform of claim 12 , wherein the second protocol is a Gen-Z protocol.

14. The data processing platform of claim 13 , further comprising:
a Gen-Z transaction layer controller coupled to the second data link layer controller; and
a PCIe transaction layer controller coupled to the first data link layer controller.

15. The data processing platform of claim 12 , further comprising:
a memory module comprising a memory, a media controller coupled to the memory, and an interface controller coupled to the media controller and the PCIe communication link, the interface controller including a second LTSSM operable to transmit and receive training ordered sets over the PCIe communication link and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the PCIe communication link.

16. The data processing platform of claim 15 , wherein the second LTSSM is part of a second a dual-protocol link controller.

17. The data processing platform of claim 15 , wherein the second LTSSM is part of a single-protocol link controller operating with the Gen-Z protocol.

18. The data processing platform of claim 15 , further comprising:
a Gen-Z memory controller coupled between the central processing unit and the dual-protocol link controller, and operable to access the memory module using Gen-Z protocol memory requests.

19. The data processing platform of claim 15 , further comprising a peripheral device coupled to the central processing unit, and communicating with the central processing unit with a PCIe protocol.

20. The data processing platform of claim 12 , in which the LTSSM transmits and receives the alternative protocol negotiation information based on a predetermined status of a control register.

Assignees

• Ati Technologies Ulc
• Advanced Micro Devices Inc

Inventors

• Caruk Gordon
• Talbot Gerald R

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/387 Primary

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title