Set buffer state instruction

Patent metadata

Field	Value
Publication number	US-10698845-B2
Application number	US-201916281879-A
Country	US
Kind code	B2
Filing date	Feb 21, 2019
Priority date	May 27, 2004
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

First claim

What is claimed is:

1. A computer program product for executing an instruction in a computing environment, said computer program product comprising:
at least one non-transitory computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
executing an instruction, the instruction having an operation code, the operation code specifying a set buffer state operation, the executing comprising:
obtaining, based on executing the instruction, an indication of one or more buffers for which state is to be set; and
setting the state of the one or more buffers based on state specified by an operand associated with the instruction, wherein the state of the one or more buffers is changed between program owned and adapter owned.

2. The computer program product of claim 1 , wherein the one or more buffers are queued direct input/output buffers.

3. The computer program product of claim 1 , wherein the instruction further comprises a first register field to be used in obtaining the indication of the one or more buffers for which state is to be set.

4. The computer program product of claim 3 , wherein the first register field includes a specification of a queue and a buffer of the queue for which state is to be set, the buffer of the queue being one of the one or more buffers for which state is to be set.

5. The computer program product of claim 4 , wherein the first register field includes a queue index that specifies the queue and a buffer number that specifies the buffer of the queue.

6. The computer program product of claim 1 , wherein the instruction further comprises a register field, the register field comprising at least one of a count of buffers having set states, or a condition code qualifier to include a condition code qualifier code set based on completing the instruction and setting a condition code.

7. The computer program product of claim 1 , wherein the instruction further comprises one or more fields used to provide the operand.

8. The computer program product of claim 1 , wherein the state of the one or more buffers is set on behalf of a guest of the computing environment, the state of the one or more buffers being stored in host storage.

9. The computer program product of claim 1 , wherein the method further comprises obtaining the instruction based on initiation of the instruction by a guest program to dynamically synchronize guest queues with host shadow copies of the queues absent host intervention.

10. A computer system for executing an instruction in a computing environment, said computer system comprising:
a memory; and
a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
executing an instruction, the instruction having an operation code, the operation code specifying a set buffer state operation, the executing comprising:
obtaining, based on executing the instruction, an indication of one or more buffers for which state is to be set; and
setting the state of the one or more buffers based on state specified by an operand associated with the instruction, wherein the state of the one or more buffers is changed between program owned and adapter owned.

11. The computer system of claim 10 , wherein the instruction further comprises a first register field to be used in obtaining the indication of the one or more buffers for which state is to be set.

12. The computer system of claim 10 , wherein the instruction further comprises a register field, the register field comprising at least one of a count of buffers having set states, or a condition code qualifier to include a condition code qualifier code set based on completing the instruction and setting a condition code.

13. The computer system of claim 10 , wherein the instruction further comprises one or more fields used to provide the operand.

14. The computer system of claim 10 , wherein the method further comprises obtaining the instruction based on initiation of the instruction by a guest program to dynamically synchronize guest queues with host shadow copies of the queues absent host intervention.

15. The computer system of claim 10 , wherein the state of the one or more buffers is set on behalf of a guest of the computing environment, the state of the one or more buffers being stored in host storage.

16. A computer-implemented method of executing an instruction in a computing environment, said computer-implemented method comprising:
executing an instruction, the instruction having an operation code, the operation code specifying a set buffer state operation, the executing comprising:
obtaining, based on executing the instruction, an indication of one or more buffers for which state is to be set; and
setting the state of the one or more buffers based on state specified by an operand associated with the instruction, wherein the state of the one or more buffers is changed between program owned and adapter owned.

17. The computer-implemented method of claim 16 , wherein the instruction further comprises a first register field to be used in obtaining the indication of the one or more buffers for which state is to be set.

18. The computer-implemented method of claim 16 , wherein the instruction further comprises a register field, the register field comprising at least one of a count of buffers having set states, or a condition code qualifier to include a condition code qualifier code set based on completing the instruction and setting a condition code.

19. The computer-implemented method of claim 16 , wherein the instruction further comprises one or more fields used to provide the operand.

20. The computer-implemented method of claim 16 , further comprising obtaining the instruction based on initiation of the instruction by a guest program to dynamically synchronize guest queues with host shadow copies of the queues absent host intervention.

Assignees

• IBM

Inventors

• Easton Janet R
• Holder William A
• Nerz Bernd
• Osisek Damian L
• Sittmann Iii Gustav E
• Tarcza Richard P
• Wyman Leslie W

Classifications

• H04W72/52

  based on load · CPC title

• H04W72/23

  in the downlink direction of a wireless link, i.e. towards a terminal · CPC title

• H04N23/57

  Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices · CPC title

• H04L47/70

  Admission control; Resource allocation · CPC title

• H04W74/002

  Transmission of channel access control information · CPC title