Inter-chip communication in a multi-chip system

Patent metadata

Field	Value
Publication number	US-10698825-B1
Application number	US-201916299291-A
Country	US
Kind code	B1
Filing date	Mar 12, 2019
Priority date	Mar 12, 2019
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

In a system-on-chip there is a local interconnect to connect local devices on the chip to one another, a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect, and a cache-coherent device. The cache-coherent device has a cache-coherency look-up table having entries for shared cache data lines. When a data access request is received via the inter-chip interconnect and the local interconnect a system-unique identifier for a request source of the data access request is generated in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip. The bit-set used to express the system-unique identifier is larger than the bit-set used to express the inter-chip request source identifier. The system-unique identifier is used with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line enabling more cache coherent devices to be supported.

First claim

We claim:

1. A system-on-chip comprising:
a local interconnect to connect local devices on the chip to one another;
a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect; and
a cache-coherent device, the cache-coherent device comprising snoop circuitry to perform cache-coherency actions and comprising a cache-coherency look-up table having entries for cache data lines corresponding to shared data items accessed by devices of the cache-coherent multi-chip system, wherein the snoop circuitry is responsive to a data access request received via the inter-chip interconnect and the local interconnect:
to generate a system-unique identifier for a request source of the data access request in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip, wherein a bit-set used to express the system-unique identifier is larger than a bit-set used to express the inter-chip request source identifier;
to identify a cache line corresponding to a data item specified in the data access request; and
to use the system-unique identifier with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line.

2. The system-on-chip of claim 1 , wherein the at least one chip of the plurality of chips comprises plural gateways to connect the chip to plural remote chips of the plurality of chips via respective plural inter-chip interconnects.

3. The system-on-chip of claim 2 , wherein the identifier indicative of the remote chip is a gateway indicator indicative of the gateway.

4. The system-on-chip of claim 1 , wherein the gateway is responsive to reception of the data access request on the inter-chip interconnect to perform a conversion of the inter-chip request source identifier into a logical device identifier for a corresponding target device of the local devices on the chip.

5. The system-on-chip of claim 4 , wherein logical device identifiers for the local devices on the chip form a contiguous set of values.

6. The system-on-chip of claim 5 , wherein the snoop circuitry is responsive to the data access request received via the inter-chip interconnect and the local interconnect to generate the system-unique identifier for the request source of the data access request by performing a translation of the identifier indicative of the remote chip into an offset value and adding the offset value to the logical device identifier.

7. The system-on-chip of claim 6 , wherein the translation is made with reference to a software programmable offset lookup table storing correspondences between identifiers indicative of respective remote chips and respective offset values.

8. The system-on-chip of claim 7 , wherein the identifier indicative of the remote chip is a gateway indicator indicative of the gateway, and the software programmable offset lookup table stores correspondences between gateway indicators and respective offset values.

9. The cache-coherent multi-chip system of claim 4 , wherein the conversion is made with reference to a software programmable logical device lookup table storing correspondences between inter-chip request source identifiers and logical device identifiers.

10. The system-on-chip of claim 1 , wherein the local interconnect is responsive to an outgoing data access request from the cache-coherent device to perform a conversion of a chip-unique device identifier of the cache-coherent device into a logical device identifier for cache-coherent device on the chip.

11. The system-on-chip of claim 10 , wherein the gateway is responsive to reception of the outgoing data access request on the local interconnect to perform a conversion of the logical device identifier for cache-coherent device on the chip into an inter-chip request source identifier for the chip.

12. The system-on-chip of claim 1 , wherein the snoop circuitry is arranged, when issuing a snoop request for the cache-coherency actions with respect to a cache line corresponding to an entry in the cache-coherency look-up table, to convert a system-unique identifier for a target of the snoop request retrieved from the cache-coherency look-up table into a logical device identifier for a target device of the snoop request.

13. The system-on-chip of claim 12 , wherein the snoop circuitry is arranged to convert the system-unique identifier for the target of the snoop request with reference to a mapping table, wherein the mapping table comprises an entry for each system-unique identifier and the entry comprises a remote bit indicative of whether the system-unique identifier corresponds to a local device on the chip or a remote device on a remote chip of the plurality of chips.

14. The system-on-chip of claim 13 , wherein the snoop circuitry is responsive to the remote bit indicating that the system-unique identifier corresponds to a remote device on a remote chip of the plurality of chips to make reference to a software programmable offset lookup table storing correspondences between identifiers indicative of respective remote chips and respective offset values to determine an identifier of the remote chip of the target of the snoop request.

15. The system-on-chip of claim 14 , wherein the identifier indicative of the remote chip is a gateway indicator indicative of a gateway connecting the chip to the remote chip of the target of the snoop request.

16. A method of operating a system-on-chip comprising:
a local interconnect to connect local devices on the chip to one another;
a gateway to connect the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect; and
a cache-coherent device, the method comprising:
performing cache-coherency actions with reference to a cache-coherency look-up table having entries for cache data lines corresponding to shared data items accessed by devices of the cache-coherent multi-chip system; and
in response to a data access request received via the inter-chip interconnect and the local interconnect:
generating a system-unique identifier for a request source of the data access request in dependence on an inter-chip request source identifier used on the inter-chip interconnect and an identifier indicative of the remote chip, wherein a bit-set used to express the system-unique identifier is larger than a bit-set used to express the inter-chip request source identifier;
identifying a cache line corresponding to a data item specified in the data access request; and
using the system-unique identifier with respect to the cache-coherency look-up table to perform the cache-coherency actions for the cache line.

17. A system-on-chip comprising:
local interconnect means for connecting local devices on the chip to one another;
gateway means for connecting the chip to a remote chip of a plurality of chips in a cache-coherent multi-chip system via an inter-chip interconnect;
cache-coherent device means for performing cache-coherency actions with reference to a cache-coherency look-up table having entries for cache data lines corresponding to shared data items accessed by devices of the cache-coherent multi-chip system,
wherein the cache coherent device means is responsive to a data access request received via the inter-chip interconnect and the local interconnect to engage:
means for generating a system-unique identifier for a request source of the data access request in dependence on an inter-chip request source identifier used on the inter-chip interconnect

Assignees

• Advanced Risc Mach Ltd

Inventors

• Ramagiri Gurunath
• Tummala Ashok Kumar
• Werkheiser Mark David
• Jalal Jamshed
• Shivakumar Premkishore
• Meyer Paul Gilbert

Classifications

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0813 Primary

  with a network or matrix configuration · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F16/9017

  using directory or table look-up (use of a directory or look-up table in file systems G06F16/13) · CPC title

• G06F12/0822 Primary

  Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831) · CPC title