High-frequency clock distribution and alignment system

Patent metadata

Field	Value
Publication number	US-10698441-B2
Application number	US-201815984841-A
Country	US
Kind code	B2
Filing date	May 21, 2018
Priority date	May 21, 2018
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.

First claim

What is claimed is:

1. A clock distribution and alignment system comprising:
a plurality of clock generators, each comprising:
a clock receiver circuit to receive a global clock signal having a first frequency, and

a clock divider circuit to divide the received global clock signal into at least one local clock signal having a frequency lower than the first frequency, wherein one of the at least one local clock signal is a tuning clock signal; and
a corresponding plurality of phase aligners, wherein each of the phase aligners are coupled to a respective one of the clock generators in a control loop, the phase aligners comprising:
a phase detector circuit to compare a phase of the tuning clock signal with a reference phase from a reference local clock signal from a different one of the local clock generators, and
a clock adjuster circuit to adjust the tuning clock signal based on result of the compared phase from the reference local clock signal, to align the phase of the tuning clock signal.

2. The system of claim 1 wherein each of the plurality of phase aligners further includes a programmable gain to adjust sensitivity of the phase detector circuit.

3. The system of claim 1 wherein the clock adjuster circuit aligns the phase of the tuning clock signal to within a certain offset amount of each other.

4. The system of claim 3 , wherein the clock adjuster circuit aligns the phase of the tuning clock signal by specifying an adjustment request to the clock receiver circuit, and the clock receiver circuit adjusts the received global clock signal according to the specified adjustment request.

5. The system of claim 4 , wherein the clock receiver circuit comprises:
a clock phase circuit to generate a plurality of delayed global clock signals from the received global clock signal; and
a multiplexer to select one of the delayed global clock signals according to the specified adjustment request.

6. The system of claim 5 , wherein the clock phase circuit comprises:
a component generator circuit to generate in-phase and quadrature components of the received global clock signal; and
a phase blender circuit to generate the plurality of delayed global clock signals by combining the in-phase and quadrature components with a corresponding plurality of different amplitude adjustments for each of the in-phase and quadrature components.

7. The system of claim 4 , wherein the clock receiver circuit comprises a pulse swallow circuit to swallow one or more pulses of the received global clock signal according to the specified adjustment request.

8. The system of claim 1 wherein the second frequency is at least 500 megahertz (MHz) and the clock divider circuit divides the received global clock signal into a plurality of divided clock signals having corresponding frequencies that are multiples of the second frequency.

9. The system of claim 1 wherein the phase detector circuit comprises a bang-bang phase detector.

10. A method of clock distribution and alignment, the method comprising:
receiving, at a clock receiver circuit of each of a plurality of dispersed clock generators, a first clock signal having a first frequency;
dividing, by a clock divider circuit of each clock generator, the received first clock signal into a second clock signal having a second frequency lower than the first frequency;
comparing, by a phase detector circuit of each of a corresponding plurality of phase aligners, the phase of the second clock signal of a respective one of the clock generators with the phase of the second clock signal of a respective other one of the clock generators; and
adjusting, by a clock adjuster circuit of each phase aligner, the received first clock signal of the respective one of the clock generators based on the compared phases of the second clock signals, to align the phases of the second clock signals.

11. The method of claim 10 , further comprising for each phase aligner:
adjusting, by a programmable gain of the phase aligner, sensitivity of the phase detector circuit so that the sensitivity of the phase detector circuit of one of the phase aligners is less than the sensitivity of the phase detector circuit of others of the phase aligners; and
aligning the phases of the second clock signals until the phases of the second clock signals of the dispersed clock generators are within a certain offset amount of each other.

12. The method of claim 10 , further comprising for each phase aligner,
adjusting, by the clock receiver circuit of the respective one of the clock generators, the received first clock signal according to a specified adjustment request, wherein for each phase aligner, the adjusting of the received first clock signal comprises specifying the adjustment request to the clock receiver circuit of the respective one of the clock generators.

13. The method of claim 12 , wherein for each phase aligner, the adjusting of the received first clock signal comprises:
generating in-phase and quadrature components of the received first clock signal;
generating a plurality of delayed first clock signals by combining the in-phase and quadrature components with a corresponding plurality of different amplitude adjustments for each of the in-phase and quadrature components; and
selecting one of the delayed first clock signals according to the specified adjustment request.

14. The method of claim 12 , wherein for each phase aligner, the adjusting of the received first clock signal comprises swallowing, by the clock receiver circuit of the respective one of the clock generators, one or more pulses of the received first clock signal according to the specified adjustment request.

15. The method of claim 10 , wherein for each of the dispersed clock generators, the second frequency is at least 500 megahertz (MHz) and the dividing of the received first clock signal comprises dividing the received first clock signal into a plurality of divided clock signals having corresponding frequencies that are multiples of the second frequency.

16. The method of claim 10 , wherein for each phase aligner,
the comparing of the phases of the second clock signals comprises:
consistently indicating which of the phases of the second clock signals is earlier than the other when the phases are offset by more than a certain offset amount; and
alternately indicating which of the phases of the second clock signals is earlier than the other when the phases are offset by less than the certain offset amount, and

the aligning of the phases of the second clock signals is to within the certain offset amount of each other.

17. A clock distribution and alignment system comprising:
a plurality of dispersed clock generators each including
a clock receiver circuit to receive and adjust a common first clock signal having a first frequency of at least 1 gigahertz (GHz), and
a clock divider circuit to divide the received first clock signal into power-of-two-divided clock signals having corresponding power-of-two-divided frequencies the same as or lower than the first frequency, the divided clock signals including a second clock signal having a second frequency lower than the first frequency;

a corresponding plurality of phase aligners each including
a phase detector circuit to compare the phase of the second clock signal of a respective one of the clock generators with the phase of the second clock signal of a respective other one of the clock generators, and
a clock adjuster circuit to use the clock receiver circuit of the respective one of the clock generators to adjust the received first clock signal of

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Cali Joseph D
• Turner Steven E

Classifications

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title