Pixel clock generating device, image writing device, and image forming apparatus

Patent metadata

Field	Value
Publication number	US-10698198-B2
Application number	US-201715834665-A
Country	US
Kind code	B2
Filing date	Dec 7, 2017
Priority date	Feb 20, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A pixel clock generating device includes a high-frequency clock generator, a comparer, a pixel clock generator, and a value switcher. The high-frequency clock generator is configured to generate a high-frequency clock. The comparer is configured to measure a time interval between a leading-end synchronizing signal and a trailing-end synchronizing signal in a main scanning and calculate an error between the time interval and a target value. The pixel clock generator is configured to generate a pixel clock based on the high-frequency clock and a pixel clock frequency and correct the pixel clock based on the error. The value switcher, including a plurality of groups of values with which the pixel clock is generated, is configured to switch between the plurality of groups of values according to a switching signal after the trailing-end synchronizing signal is inputted, the comparer calculates the error, and the pixel clock generator corrects the pixel clock.

First claim

What is claimed is:

1. A pixel clock generating device comprising:
a high-frequency clock generator configured to generate a high-frequency clock;
a comparer configured to measure a time interval between a leading-end synchronizing signal and a trailing-end synchronizing signal in a main scanning and calculate an error between the time interval and a target value;
a pixel clock generator configured to generate a pixel clock based on the high-frequency clock and a pixel clock frequency and correct the pixel clock based on the error; and
a value switcher including a plurality of groups of values with which the pixel clock is generated, each of the plurality of groups of values associated with a-faces of a polygonal mirror, the polygonal mirror including at least three faces,
the value switcher configured to switch between the plurality of groups of values according to a switching signal based on the trailing-end synchronizing signal being inputted, the comparer calculating the error, and the pixel clock generator correcting the pixel clock.

2. The pixel clock generating device according to claim 1 , wherein the value switcher is configured to complete switching between the plurality of groups of values according to the switching signal before a next leading-end synchronizing signal is inputted.

3. The pixel clock generating device according to claim 1 , wherein the value switcher is configured to:
latch the switching signal inputted until the comparer completes calculating the error and the pixel clock generator completes correcting the pixel clock; and
then output the switching signal.

4. The pixel clock generating device according to claim 1 , wherein the plurality of groups of values is identically configured.

5. The pixel clock generating device according to claim 1 , wherein the pixel clock generator is further configured to average a plurality of error values and correct the pixel clock based on the average of the plurality of error values.

6. The pixel clock generating device according to claim 1 , wherein the pixel clock generator is further configured to set the pixel clock frequency based on the error and the target value.

7. An image writing device comprising:
at least one semiconductor laser configured to form an electrostatic latent image on a photoconductor;
a high-frequency clock generator configured to generate a high-frequency clock;
a comparer configured to measure a time interval between a leading-end synchronizing signal and a trailing-end synchronizing signal in a main scanning and calculate an error between the time interval and a target value;
a pixel clock generator configured to generate a pixel clock based on the high-frequency clock and a pixel clock frequency and correct the pixel clock based on the error; and
a value switcher including a plurality of groups of values with which the pixel clock is generated, each of the plurality of groups of values associated with a-faces of a polygonal mirror, the polygonal mirror including at least three faces,
the value switcher configured to switch between the plurality of groups of values according to a switching signal based on the trailing-end synchronizing signal being inputted, the comparer calculating the error, and the pixel clock generator correcting the pixel clock.

8. An image forming apparatus comprising the image writing device according to claim 7 .

9. The image writing device according to claim 7 , wherein the value switcher is configured to complete switching between the plurality of groups of values according to the switching signal before a next leading-end synchronizing signal is inputted.

10. The image writing device according to claim 7 , wherein the value switcher is configured to:
latch the switching signal inputted until the comparer completes calculating the error and the pixel clock generator completes correcting the pixel clock; and
then output the switching signal.

11. The image writing device according to claim 7 , wherein the plurality of groups of values is identically configured.

12. The image writing device according to claim 7 , wherein the pixel clock generator is further configured to average a plurality of error values and correct the pixel clock based on the average of the plurality of error values.

13. The image writing device according to claim 7 , wherein the pixel clock generator is further configured to set the pixel clock frequency based on the error and the target value.

14. An image writing device for writing images of a plurality of colors, the image writing device comprising a pixel clock generating device for each of the plurality of colors, the pixel clock generating device comprising:
a high-frequency clock generator configured to generate a high-frequency clock;
a comparer configured to measure a time interval between a leading-end synchronizing signal and a trailing-end synchronizing signal in a main scanning and calculate an error between the time interval and a target value;
a pixel clock generator configured to generate a pixel clock based on the high-frequency clock and a pixel clock frequency and correct the pixel clock based on the error; and
a value switcher including a plurality of groups of values with which the pixel clock is generated, each of the plurality of groups of values associated with a-faces of a polygonal mirror, the polygonal mirror including at least three faces,
the value switcher configured to switch between the plurality of groups of values according to a switching signal based on the trailing-end synchronizing signal being inputted, the comparer calculating the error, and the pixel clock generator correcting the pixel clock.

15. The image writing device according to claim 14 , wherein the pixel clock generating device for each of the plurality of colors is configured to switch between the plurality of groups of values according to the switching signal at a time different from each other.

16. The image writing device according to claim 14 , wherein the value switcher is configured to complete switching between the plurality of groups of values according to the switching signal before a next leading-end synchronizing signal is inputted.

17. The image writing device according to claim 14 , wherein the value switcher is configured to:
latch the switching signal inputted until the comparer completes calculating the error and the pixel clock generator completes correcting the pixel clock; and
then output the switching signal.

18. The image writing device according to claim 14 , wherein the plurality of groups of values is identically configured.

19. The image writing device according to claim 14 , wherein the pixel clock generator is further configured to average a plurality of error values and correct the pixel clock based on the average of the plurality of error values.

20. The image writing device according to claim 14 , wherein the pixel clock generator is further configured to set the pixel clock frequency based on the error and the target value.

Assignees

• Tokuda Masashi
• Ricoh Co Ltd

Inventors

• Tokuda Masashi

Classifications

• G03G15/043

  with means for controlling illumination or exposure (G03G15/041 takes precedence) · CPC title

• G02B26/122

  Control of the scanning speed of the polygonal mirror · CPC title

• B41J2/471

  using dot sequential main scanning by means of a light deflector, e.g. a rotating polygonal mirror · CPC title

• H04N1/053

  in main scanning direction, e.g. synchronisation of line start or picture elements in a line · CPC title

• H04N1/00745

  Detecting the leading or trailing ends of a moving sheet · CPC title