Method and apparatus of digital beamforming for a radar system

Patent metadata

Field	Value
Publication number	US-10698083-B2
Application number	US-201715686630-A
Country	US
Kind code	B2
Filing date	Aug 25, 2017
Priority date	Aug 25, 2017
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A system and method of digital beamforming for a monobit phased array radar system includes providing a plurality of monobit analog signals received by at least one antenna to at least one field programmable gate array (FPGA). A plurality of monobit SerDes transceivers within the FPGA convert the plurality of monobit analog signals into a plurality of multibit digital signals, each of the multibit digital signals being modified according to a digital signal conditioning value to calibrate, phase align, and synchronize the digital signals. A digital beam is formed by coherently combining the plurality of digital signals within the FPGA.

First claim

What is claimed is:

1. A method of digital beamforming for a monobit phased array radar system, comprising:
providing a plurality of monobit analog signals received by at least one antenna to at least one digital signal processing chip interfacing the at least one antenna, wherein the at least one digital signal processing chip is a field programmable gate array (FPGA);
determining, by at least one processing module, a digital signal conditioning value for each of the monobit analog signals by using delta sigma modulation, DC offset modulation, and coherently summing a plurality of elements for dynamic range;
converting, by a plurality of monobit SerDes transceivers within the at least one digital signal processing chip, the plurality of monobit analog signals into a plurality of multibit digital signals, each of the multibit digital signals being modified according to the digital signal conditioning value of the respective monobit analog signal to phase align and synchronize the digital signals; and
forming a digital beam by coherently combining the plurality of digital signals within the digital signal processing chip.

2. The method of claim 1 , wherein in the step of providing the analog signals, the at least one digital signal processing chip directly interfaces with the at least one antenna.

3. The method of claim 1 , wherein the at least one processing module is part of the digital signal processing chip.

4. The method of claim 1 , wherein each digital signal conditioning value is created, at least in part, by determining a monobit time delay to compensate for response errors attributable to analog input pins of the SerDes transceivers to contribute to formation of a desired beam.

5. The method of claim 1 , wherein the SerDes transceivers are used in a loop back configuration to create a Sigma Delta receiver.

6. The method of claim 1 , further comprising during a receiving mode, combining phase aligned multibit digital signals to achieve signal processing gain.

7. The method of claim 1 , further comprising during a transmitting mode, combining power of multibit digital signals to achieve coherent gain.

8. The method of claim 1 , further comprising utilizing analog input SerDes transceiver pins of the at least one digital signal processing chip and the monobit SerDes transceivers as virtual analog-to-digital or digital-to-analog converters.

9. The method of claim 1 , wherein in the step of forming a digital beam, at least some of the plurality of digital signals come from a separate digital signal processing chip.

10. An ultra-wideband digital phased array radar system, comprising:
an antenna array comprising a plurality of antenna elements configured to receive a plurality of monobit analog signals; and
at least one digital signal processing chip interfacing the antenna array, each digital signal processing chip being a field programmable gate array (FPGA) comprising an integrated all digital chip including a plurality of monobit SerDes transceivers and a digital beamforming unit, such that the digital signal processing chip is configured to:
determine, for each monobit analog signal, a respective digital signal conditioning value by using delta sigma modulation, DC offset modulation, and coherently summing a plurality of elements for dynamic range;
convert, through use of the plurality of monobit SerDes transceivers, the plurality of monobit analog signals into a plurality of digital signals, each of the digital signals being modified according to its respective digital signal conditioning value to phase align and synchronize the digital signals; and
form a digital beam by coherently combining, within the digital beamforming unit, the plurality of digital signals.

11. The system of claim 10 , wherein the at least one digital signal processing chip interfaces directly with the antenna elements.

Assignees

• Raytheon Co

Inventors

• Thompson Daniel
• Marr Harry B
• Robinson Ian
• Caldwell Jeffrey

Classifications

• G01S7/032 Primary

  Constructional details for solid-state radar subsystems · CPC title

• G01S7/4026

  Antenna boresight · CPC title

• G01S2013/0254

  Active array antenna · CPC title

• H01Q3/2682

  Time delay steered arrays · CPC title

• H01Q3/2605

  Array of radiating elements provided with a feedback control over the element weights, e.g. adaptive arrays · CPC title