Lock-in amplifier, integrated circuit and portable measurement device including the same

Patent metadata

Field	Value
Publication number	US-10698013-B2
Application number	US-201615360196-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Nov 27, 2015
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A lock-in amplifier includes a clock signal generator configured to generate a first demodulation clock signal and a second demodulation clock signal having a phase difference of 90 degrees and a same demodulation frequency; and a detector configured to, based on an input signal, the first demodulation clock signal, and the second demodulation clock signal, provide an offset voltage corresponding to an offset of the lock-in amplifier in a first operation mode, and provide a first output voltage and a second output voltage, each of which correspond to a demodulation frequency component of the input signal in a second operation mode.

First claim

What is claimed is:

1. A lock-in amplifier comprising:
a clock signal generator configured to generate a first demodulation clock signal and a second demodulation clock signal having a phase difference of 90 degrees and a same demodulation frequency; and
a detector configured to, based on an input signal, the first demodulation clock signal, and the second demodulation clock signal,
provide an offset voltage corresponding to an offset of the lock-in amplifier in a first operation mode, and
provide a first output voltage and a second output voltage, each of which correspond to a demodulation frequency component of the input signal in a second operation mode,

wherein the detector includes at least one mixer and generates the offset voltage, the first output voltage and the second output voltage based on an operation mode using the at least one mixer.

2. The lock-in amplifier of claim 1 , wherein the detector includes a mixer and the demodulation frequency component of the input signal is determined by
Vo =[( VOX−VOS ) 2 +( VOY−VOS ) 2 ] 1/2 ,
where Vo is an output of the lock-in amplifier corresponding to the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage and VOS is the offset voltage.

3. The lock-in amplifier of claim 1 , wherein the detector includes a first mixer and a second mixer, and is configured to,
generate a first offset voltage and a second offset voltage,
generate the first offset voltage and the first output voltage sequentially based on an operation mode using the first mixer, and
generate the second offset voltage and the second output voltage sequentially based on an operation mode using the second mixer.

4. The lock-in amplifier of claim 3 , wherein the demodulation frequency component of the input signal is determined by
Vo =[( VOX−VOSX ) 2 +( VOY−VOSY ) 2 ] 1/2 ,
where Vo is an output of the lock-in amplifier corresponding to the demodulation frequency component, VOX is the first output voltage, VOY is the second output voltage, VOSX is the first offset voltage, and VOSY is the second offset voltage.

5. The lock-in amplifier of claim 1 , wherein the detector comprises:
an amplification circuit configured to amplify the input signal to output an amplified signal in the second operation mode;
a mixing circuit configured to,
multiply the amplified signal and the first demodulation clock signal to output a first rectified signal in the second operation mode, and
multiply the amplified signal and the second demodulation clock signal to output a second rectified signal in the second operation mode; and

a filtering circuit configured to,
filter the first rectified signal to generate the first output voltage in the second operation mode, and
filter the second rectified signal to generate the second output voltage in the second operation mode.

6. The lock-in amplifier of claim 5 , wherein the mixing circuit comprises:
a mixer, the mixer including,
a first input terminal configured to receive the amplified signal,
a second input terminal configured to receive the first demodulation clock signal and the second demodulation clock signal sequentially in the second operation mode, and
an output terminal configured to output the first rectified signal and the second rectified signal sequentially in the second operation mode.

7. The lock-in amplifier of claim 6 , wherein the filtering circuit comprises:
a low pass filter connected to the output terminal of the mixer and configured to output the first output voltage and the second output voltage sequentially in the second operation mode.

8. The lock-in amplifier of claim 6 , further comprising:
a clock selector configured to select one of the first demodulation clock signal and the second demodulation clock signal to provide a selected demodulation clock signal to the second input terminal of the mixer.

9. The lock-in amplifier of claim 5 , wherein the mixing circuit comprises:
a first mixer, the first mixer including,
a first input terminal configured to receive the amplified signal,
a second input terminal configured to receive the first demodulation clock signal, and
a first output terminal configured to output the first rectified signal; and

a second mixer, the second mixer including,
a third input terminal configured to receive the amplified signal,
a fourth input terminal configured to receive the second demodulation clock signal, and
a second output terminal configured to output the second rectified signal.

10. The lock-in amplifier of claim 9 , wherein the filtering circuit includes:
a first low pass filter connected to the first output terminal and configured to output a first offset voltage in the first operation mode and output the first output voltage in the second operation mode; and
a second low pass filter connected to the second output terminal and configured to output a second offset voltage in the first operation mode and output the second output voltage in the second operation mode.

11. The lock-in amplifier of claim 5 , wherein the detector further comprises:
an input circuit configured to block the input signal from being applied to the amplification circuit in the first operation mode in response to a mode signal.

12. The lock-in amplifier of claim 11 , wherein the filtering circuit is configured to generate the offset voltage while the input signal is blocked by the input circuit from being applied to the amplification circuit.

13. The lock-in amplifier of claim 1 , wherein the clock signal generator includes:
a plurality of flip-flops configured to generate the first demodulation clock signal and the second demodulation clock signal based on a reference clock signal having a frequency corresponding to N times the demodulation frequency, where N is a natural number.

14. The lock-in amplifier of claim 1 , wherein the clock signal generator includes:
a first flip-flop, the first flip-flop including,
a clock terminal configured to receive a reference clock signal,
a non-inversion output terminal configured to generate a first clock signal,
an inversion output terminal configured to generate a second clock signal, and
a data terminal connected to the inversion output terminal of the first flip-flop;

a second flip-flop, the second flip-flop including,
a clock terminal configured to receive the first clock signal,
a non-inversion output terminal configured to generate the first demodulation clock signal,
an inversion output terminal, and
a data terminal connected to the inversion output terminal of the second flip-flop; and

a third flip-flop, the third flip-flop including,
a clock terminal configured to receive the second clock signal,
a non-inversion output terminal configured to generate the second demodulation clock signal,
an inversion output terminal, and
a data terminal connected to the inversion output terminal of the third flip-flop.

15. The lock-in amplifier of claim 14 , wherein a frequency of the reference clock signal is four times the demodulation frequency.

16. The lock-in amplifier of claim 1 , wherein the clock signal generator includes:
a first flip-flop, the first flip-flop including,
a clock terminal configured to receive a reference clock signal,
a non-inversion output terminal configured to generate the first demodulation clock signal,
an inversion output terminal, and
a data terminal connected to the inversion output terminal of the first flip-flop; and

a second flip-flop, the second flip-flop including,
a clock terminal configured to receiv

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Dae-Young
• Park Jae-Jin
• Lim Dong-Hyuk

Classifications

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03D3/007

  by converting the oscillations into two quadrature related signals (H03D3/245 takes precedence) · CPC title

• H03F2200/261

  Amplifier which being suitable for instrumentation applications · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title