Sam assisted selective e-less plating on packaging materials

Patent metadata

Field	Value
Publication number	US-10697065-B2
Application number	US-201615769699-A
Country	US
Kind code	B2
Filing date	Aug 8, 2016
Priority date	Nov 30, 2015
Publication date	Jun 30, 2020
Grant date	Jun 30, 2020

Abstract

A method including activating an area of a polymer layer on a substrate with electromagnetic radiation; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with the self-assembled monolayer; and reacting the self-assembled monolayer with a conductive material. A method including activating an area of a polymer dielectric layer on a substrate with electromagnetic radiation, the area selected for an electrically conductive line; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with a catalyst; and electroless plating a conductive material on the self-assembled monolayer.

First claim

What is claimed is:

1. An integrated circuit chip package substrate comprising a plurality of conductive lines formed on a radiation-activated dielectric material, the conductive lines formed of conductive material chemically bonded to the dielectric material through a self-assembled monolayer.

2. The substrate of claim 1 , wherein the conductive material is chemically bonded to the self-assembled monolayer through a catalyst.

3. The substrate of claim 1 , wherein the dielectric material comprises a polymer material.

4. A method comprising:
activating an area of a polymer layer on a package substrate by exposing portions of a surface of the polymer layer to electromagnetic radiation;
modifying the activated area;
forming a self-assembled monolayer on the modified active area;
reacting the self-assembled monolayer with a catalyst; and
reacting the self-assembled monolayer with a conductive material.

5. The method of claim 4 , wherein modifying the activated area comprises forming a hydroxyl ion rich area.

6. The method of claim 4 , wherein the self-assembled monolayer comprises a functional group operable to react with the catalyst.

7. The method of claim 6 , wherein the functional group comprises one of an amine moiety, a sulfhydryl moiety and a pyridil moiety.

8. The method of claim 4 , wherein the catalyst is a metal and reacting the self-assembled monolayer with a conductive material comprises reducing the catalyst in a bath comprising a reducing agent and an ionic form of the conductive material.

9. The method of claim 8 , wherein reacting the self-assembled monolayer with a conductive material comprises reducing the state of the ionic form of conductive material.

10. A method comprising:
activating an area of a polymer dielectric layer on a substrate by exposing portions of a surface of the polymer layer to electromagnetic radiation, the area selected for an electrically conductive line;
modifying the activated area;
forming a self-assembled monolayer on the modified active area;
reacting the self-assembled monolayer with a catalyst; and
electroless plating a conductive material on the self-assembled monolayer.

11. The method of claim 10 , wherein modifying the activated area comprises forming a hydroxyl ion rich area.

12. The method of claim 10 , wherein the self-assembled monolayer comprises a functional group operable to react with the catalyst.

13. The method of claim 12 , wherein the functional group comprises one of an amine moiety, a sulfhydryl moiety and a pyridil moiety.

14. The method of claim 10 , wherein the catalyst comprises palladium.

15. The method of claim 10 , wherein electroless plating a conductive material comprises reducing the catalyst in a bath comprising a reducing agent that is oxidized.

16. The method of claim 15 , wherein the bath comprises an ionic form of the conductive material in an oxidized state and electroless plating a conductive material comprises reducing the state of the ionic form of the conductive material.

17. The method of claim 10 , wherein the substrate comprises a package substrate.

Assignees

• Intel Corp

Inventors

• Hua Fay
• Maestre Caro Aranzazu

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• C23C18/165

  Multilayered product (layered product B32B) · CPC title

• H05K3/4629

  laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets · CPC title

• C23C18/2006 Primary

  by other methods than those of C23C18/22 - C23C18/30 · CPC title