Receiver for a telecommunication system

Patent metadata

Field	Value
Publication number	US-10693491-B2
Application number	US-201916392899-A
Country	US
Kind code	B2
Filing date	Apr 24, 2019
Priority date	Oct 25, 2016
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

First claim

The invention claimed is:

1. A receiver, comprising:
an analog baseband (ABB) filter stage including an ABB filter stage input configured to receive an analog baseband (BB) signal and an ABB filter stage output configured to provide a filtered analog BB signal;
an analog-to-digital converter (ADC) stage, including:
an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal;
an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital (A/D) conversion of the ADC input signal to derive the digital BB signal; and
a summation node at the ADC stage input;

a first feedback path configured to feedback the ADC input signal to the ABB filter stage;
a second feedback path configured to feedback the digital BB signal to the ABB filter stage comprises a first feedback digital to analog (D/A) converter; and
a third feedback path configured to feedback the digital BB signal to the summation node at the ADC stage input, wherein the third feedback path comprises a second feedback D/A converter.

2. The receiver according to claim 1 , wherein the first feedback path is analog.

3. The receiver according to claim 1 , wherein the second feedback path comprises a delay element.

4. The receiver according to a claim 1 , wherein the ABB filter stage comprises a first summation node, a first integrator, a second summation node and a second integrator;
wherein the first summation node is configured to receive the analog BB signal and to provide a first sum signal to the first integrator;
wherein the first integrator is configured to integrate the first sum signal to derive a first integrated signal;
wherein the second summation node is configured to receive the first integrated signal and to provide a second sum signal to the second integrator;
wherein the second integrator is configured to integrate the second sum signal to derive the filtered analog BB signal;
wherein each summation node is configured to also receive the signal from one of the first feedback path and the second feedback path; and
wherein each summation node is configured to sum the signals input to the respective summation node.

5. The receiver according to claim 4 , wherein the first summation node is configured to receive the signal from the first feedback path and the second summation node is configured to receive the signal from the second feedback path.

6. The receiver according to claim 4 , wherein the ADC stage comprises a third integrator coupled between the ADC stage input and the ADC input.

7. The receiver according to claim 6 , wherein the summation node at the ADC stage input is configured to sum the signal from the third feedback path and the filtered analog BB signal and to provide a resulting third sum signal to the third integrator.

8. The receiver according to claim 4 , wherein the ABB filter stage comprises a fourth feedback path connected between the first integrator output of the first integrator and the first summation node.

9. The receiver according to claim 4 , further comprising a fifth feedback back path configured to feedback the filtered analog BB signal to the first summation node.

10. The receiver according to claim 9 , wherein the fifth feedback path is analog.

11. The receiver according to claim 9 , wherein at least one of the first feedback path, the second feedback path, the third feedback path, the fourth feedback path, or the fifth feedback path is switchable.

12. The receiver according to claim 11 , wherein the receiver is configured to selectively switch on and switch off the first to fifth feedback paths in dependence on the signal type of the received analog BB signal.

13. A communication device for a wireless communication system, the communication device comprising a receiver comprising:
an analog baseband (ABB) filter stage including an ABB filter stage input configured to receive an analog baseband (BB) signal and an ABB filter stage output configured to provide a filtered analog BB signal;
an analog-to-digital converter (ADC) stage, including:
an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal;
an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital (A/D) conversion of the ADC input signal to derive the digital BB signal; and
a summation node at the ADC stage input;

a first feedback path configured to feedback the ADC input signal to the ABB filter stage;
a second feedback path configured to feedback the digital BB signal to the ABB filter stage; and
a third feedback path configured to feedback the digital BB signal to the summation node at the ADC stage input, wherein the third feedback path comprises a second feedback D/A converter.

14. The communication device of claim 13 , wherein the first feedback path is analog.

15. The communication device of claim 13 , wherein the second feedback path comprises a first feedback digital-to-analog (D/A) converter.

16. The communication device of claim 13 , wherein the second feedback path comprises a delay element.

17. The communication device of claim 13 , wherein the ABB filter stage comprises a first summation node, a first integrator, a second summation node and a second integrator,
wherein the first summation node is configured to receive the analog BB signal and to provide a first sum signal to the first integrator,
wherein the first integrator is configured to integrate the first sum signal to derive a first integrated signal,
wherein the second summation node is configured to receive the first integrated signal and to provide a second sum signal to the second integrator,
wherein the second integrator is configured to integrate the second sum signal to derive the filtered analog BB signal,
wherein each summation node is configured to also receive the signal from one of the first feedback path and the second feedback path, and
wherein each summation node is configured to sum the signals input to the respective summation node.

18. The communication device of claim 17 , wherein the first summation node is configured to receive the signal from the first feedback path and the second summation node is configured to receive the signal from the second feedback path.

19. The communication device of claim 17 , wherein the ADC stage comprises a third integrator coupled between the ADC stage input and the ADC input.

Assignees

• Huawei Tech Co Ltd

Inventors

• Koli Kimmo

Classifications

• Y02D30/70

  in wireless communication networks · CPC title

• H04W52/0209

  in terminal devices · CPC title

• H04B1/16 Primary

  Circuits · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title