Signals for the control of power devices

Patent metadata

Field	Value
Publication number	US-10693454-B2
Application number	US-201815988509-A
Country	US
Kind code	B2
Filing date	May 24, 2018
Priority date	May 24, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

In some examples, a device includes a gate driver circuit and a control circuit configured to generate a first signal and a second signal, a duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape, and a duty cycle of the second signal encoding a phase angle of the electrical current. The control circuit is configured to deliver the first and second signals to the gate driver circuit, which is configured to determine a duty cycle of a driver signal as a function of the first signal and of the second signal. The gate driver circuit is also configured to deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load.

First claim

The invention claimed is:

1. A device comprising:
a gate driver circuit; and
a control circuit configured to:
generate a first signal including a duty cycle equal to a duration of a high pulse of the first signal divided by a duration of a period of the first signal, the duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape,
generate a second signal including a duty cycle equal to a duration of a high pulse of the second signal divided by a duration of a period of the second signal, the duty cycle of the second signal encoding a phase angle of the electrical current, and
deliver the first signal and the second signal to the gate driver circuit, wherein the gate driver circuit is configured to:
determine a duty cycle of a driver signal as a function of the first signal and of the second signal, and
deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load,
wherein the driver signal is a pulse-width modulation (PWM) signal,
wherein at least one of the first signal or the second signal has a frequency that is N times a frequency of the PWM signal, and
wherein N is an integer greater than or equal to two.

2. The device of claim 1 , wherein a frequency of the driver signal is encoded as a function of a frequency of the first signal, as a function of a frequency of the second signal, or as a function of both the frequency of the first signal and the frequency of the second signal.

3. The device of claim 1 , wherein the duty cycle of the first signal is representative of a ratio between the amplitude of the electrical current and a predetermined maximum amplitude.

4. The device of claim 1 , wherein the duty cycle of the second signal is representative of a ratio between the phase angle of the electrical current and a predetermined angle value.

5. The device of claim 4 , wherein the predetermined angle value is 90 degrees, 180 degrees, or 360 degrees.

6. The device of claim of claim 1 , wherein the gate driver circuit is further configured to:
determine, based on the duty cycle of the second signal, a factor, wherein a numerical value of the factor is comprised between zero and one, and
determine the duty cycle of the driver signal as a result of multiplication of the duty cycle of the first signal and the factor.

7. The device of claim 6 ,
wherein the duty cycle of the second signal is representative of a ratio between the phase angle of the electrical current and a predetermined angle value, and
wherein the gate driver circuit is configured to determine the factor by at least:
determining the phase angle of the electrical current based on the duty cycle of the second signal and the predetermined angle value, and
determining, using a trigonometric function or an approximation thereof, the factor as an output of the trigonometric function or the approximation using the phase angle of the electrical current as an input of the trigonometric function or the approximation.

8. The device of claim 1 , wherein the first signal and the second signal have different respective frequencies.

9. The device of claim 1 ,
wherein the driver signal is a first driver signal of three driver signals that further includes a second driver signal and a third driver signal,
wherein the switch is a first switch of a plurality of switches that includes three switches,
wherein the electrical current is a first electrical current of three electrical currents that further includes a second electrical current and a third electrical current, and
wherein the gate driver circuit is further configured to:
determine respective duty cycles of the three driver signals as a function of the first signal and the second signal, and
deliver the three driver signals to the three switches to cause the three switches to deliver three respective electrical currents to the electrical load, each having a sinusoidal shape, the three electrical currents having respective phase angles that are offset one relative to the other by a predetermined amount.

10. The device of claim 9 , wherein the gate driver circuit is configured to:
determine a duty cycle of the second driver signal based on the first signal, on the second signal, and on the respective predetermined amount by which the second electrical current is offset relative to first electrical current, and
determine a duty cycle of the third driver signal based on the first signal, on the second signal, and on the respective predetermined amount by which the third electrical current is offset relative to the first electrical current.

11. The device of claim 1 , wherein at least one of the first signal or the second signal encodes side information for the gate driver circuit in addition to the phase angle of the electrical current and the amplitude of the electrical current.

12. The device of claim 11 , wherein the side information is encoded using a presence or an absence of one or more pulses located in a subinterval of cycles of the at least one of the first signal or the second signal.

13. The device of claim 11 , wherein the first signal is phase-shifted relative to the second signal by a phase shift, and wherein the phase shift encodes the side information for the gate driver circuit.

14. The device of claim 11 , wherein the electrical load includes an electric motor including a rotor, and wherein the side information defines a direction of rotation for the rotor and causes the gate driver circuit to deliver the driver signal to the switch to cause the rotor to rotate in the direction of rotation defined by the side information.

15. A device comprising:
a gate driver circuit; and
a control circuit configured to:
generate a first signal including a duty cycle equal to a duration of a high pulse of the first signal divided by a duration of a period of the first signal, the duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape,
generate a second signal including a duty cycle equal to a duration of a high pulse of the second signal divided by a duration of a period of the second signal, the duty cycle of the second signal encoding information, the first signal being phase-shifted relative to the second signal by a phase shift encoding a phase angle of the electrical current, and
deliver the first signal and the second signal to the gate driver circuit, wherein the gate driver circuit is configured to:
determine, based on the duty cycle of the second signal, a factor, wherein a numerical value of the factor is comprised between zero and one,
determine a duty cycle of a driver signal as a result of multiplication of the duty cycle of the first signal and the factor, and
deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load.

16. The device of claim 15 , wherein each cycle of the second signal includes a subinterval, a duty cycle of the subinterval of the second signal encoding the information.

17. A device comprising:
a gale driver circuit; and
a control circuit configured to:
generate a first signal including a duty cycle equal to a duration of a high pulse of the first signal divided by a duration of a period of the first signal, the duty cycle of the first signal encoding a phase angle of an electrical current having a sinusoidal shape,
generate a second signal including a duty cycle equal to a duration of a high pulse of the second signal divided by a duration of a period of

Assignees

• Infineon Technologies Austria Ag

Inventors

• Bernacchia Giuseppe
• Cox David Grant

Classifications

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H02P27/085

  wherein the PWM mode is adapted on the running conditions of the motor, e.g. the switching frequency · CPC title

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H03K17/56 Primary

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title