Magnetic tunnel junction ring oscillator with tunable frequency and methods for operating the same

Patent metadata

Field	Value
Publication number	US-10693445-B1
Application number	US-201916243433-A
Country	US
Kind code	B1
Filing date	Jan 9, 2019
Priority date	Jan 9, 2019
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

Provided are integrated circuits that include one or more magnetic tunnel junction ring oscillator(s) with tunable frequency and methods for operating the same. Accordingly, an integrated circuit is provided that includes a ring oscillator. The ring oscillator includes an input voltage terminal, an output voltage terminal, and an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal. Each of the at least three inverters includes an NMOS transistor and one or more magnetic tunnel junctions (MTJs) disposed electrically in series with the NMOS transistor. The NMOS transistor of each of the at least three inverters is selectively tunable with regard to either or both of its threshold voltage and its effective channel width.

First claim

What is claimed is:

1. An integrated circuit comprising:
a ring oscillator, wherein the ring oscillator comprises:
an input voltage terminal;
an output voltage terminal; and
an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal, each of the at least three inverters comprising a first N-type metal oxide semiconductor transistor, a second N-type metal oxide semiconductor transistor, and one or more magnetic tunnel junctions disposed electrically in series with the first N-type metal oxide semiconductor transistor and electrically in series with the second N-type metal oxide semiconductor transistor,
wherein the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor of each of the at least three inverters are selectively tunable with regard to either or both of a threshold voltage and an effective channel width.

2. The integrated circuit of claim 1 , wherein the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor of each of the at least three inverters are selectively tunable with regard to the threshold voltage.

3. The integrated circuit of claim 1 , wherein the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor of each of the at least three inverters are selectively tunable with regard to the effective channel width.

4. The integrated circuit of claim 1 , wherein the first N-type metal oxide semiconductor transistor and the second N-type metal oxide semiconductor transistor of each of the at least three inverters are selectively tunable with regard to both the threshold voltage and the effective channel width.

5. The integrated circuit of claim 1 , wherein each of the at least three inverters is coupled to a voltage source (V SS ) and a voltage drain of (VDD), and the first N-type metal oxide semiconductor transistor, the second N-type metal oxide semiconductor transistor, and the one or more magnetic tunnel junctions of each of the at least three inverters are disposed electrically in series with one another from the voltage source to the voltage drain.

6. The integrated circuit of claim 1 , wherein at least one of the at least three inverters comprises a plurality of magnetic tunnel junctions.

7. The integrated circuit of claim 6 , wherein the at least one of the at least three inverters is coupled to a voltage source (V SS ) and a number of voltage drains (VDD) equivalent in number to the number of magnetic tunnel junctions, wherein each magnetic tunnel junction of the plurality of magnetic tunnel junctions is coupled to a respective voltage drain of the number of voltage drains.

8. The integrated circuit of claim 6 , wherein at least one of the magnetic tunnel junctions from the plurality of magnetic tunnel junctions differs from another of the magnetic tunnel junctions from the plurality of magnetic tunnel junctions with regard to materials and/or dimensions.

9. The integrated circuit of claim 1 comprising three or five inverters.

10. The integrated circuit of claim 1 , wherein the ring oscillator excludes P-type metal oxide semiconductor transistors.

11. A method of operating a ring oscillator disposed on an integrated circuit, wherein the ring oscillator comprises:
an input voltage terminal;
an output voltage terminal; and
an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal, each of the at least three inverters comprising an N-type metal oxide semiconductor transistor and one or more magnetic tunnel junctions disposed electrically in series with the N-type metal oxide semiconductor transistor, and the N-type metal oxide semiconductor transistor of each of the at least three inverters selectively tunable with regard to either or both of a threshold voltage and an effective channel width, and
wherein the method comprises:
sending a first control signal to at least one of the N-type metal oxide semiconductor transistors to operate at a selected tuning level, with regard to either or both of the threshold voltage and the effective channel width, of a plurality of tuning levels;
sending a second control signal to at least one of the one or more magnetic tunnel junctions to operate at a selected state, either parallel or anti-parallel; and
sending a third control signal to the N-type metal oxide semiconductor transistor of one of the at least three inverters to operate in an inactive or “off” state.

12. The method of claim 11 , wherein the ring oscillator is configured such that at least one of the at least three inverters comprises a plurality of magnetic tunnel junctions, the at least one of the at least three inverters is coupled to a voltage source (Vss) and a number of voltage drains (VDD) equivalent in number to the number of the plurality of magnetic tunnel junctions, and wherein each one or more magnetic tunnel junction of the plurality of magnetic tunnel junctions is coupled to a respective voltage drain of the number of voltage drains, and the method further comprising:
sending a fourth control signal to at least one of the plurality of magnetic tunnel junctions to operate at a selected state, either parallel or anti-parallel, wherein the at least one of the one or more magnetic tunnel junctions and the at least one of the plurality of magnetic tunnel junctions are provided as part of the same inverter of the at least three inverters.

13. The method of claim 11 , wherein the first and second signals are sent to a ring oscillator comprising three or five inverters.

14. The method of claim 11 , wherein the first and second signals are sent to a ring oscillator excluding P-type metal oxide semiconductor transistors.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Liu Bin
• Toh Eng Huat

Classifications

• H10N59/00

  Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 (MRAM devices H10B61/00) · CPC title

• H03K3/45

  by the use, as active elements, of non-linear magnetic or dielectric devices · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/80

  Constructional details · CPC title

• H01F10/3286

  Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy · CPC title