Transformer

Patent metadata

Field	Value
Publication number	US-10693387-B2
Application number	US-201414911245-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Sep 12, 2013
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A transformer is provided between a power supply and a load, and includes a front stage circuit and a rear stage circuit each having a function of performing switching so as to alternately invert a polarity of output relative to input. The transformer further includes: a series unit provided in at least one of both circuits and composed of a pair of reactance elements connected in series to each other via a connection point; and a switch device which, with both ends of the series unit serving as a first port, causes a part between one end of the series unit and the connection point, and a part between the other end of the series unit and the connection point, to serve as a second port alternately through switching while inverting a polarity, and executes power transmission from the first port to the second port or vice versa.

First claim

The invention claimed is:

1. A transformer provided between a power supply and a load to execute voltage transformation from AC to AC, the transformer not having a core and windings, the transformer comprising:
a front stage circuit having input ports (P 1 and P 2 ) on a front end side connected to the power supply, and output ports (P 3 and P 4 ) on a rear end side; and
a rear stage circuit having output ports (P 7 and P 8 ) on a rear end side connected to the load, and input ports (P 5 and P 6 ) on a front end side, wherein
as the front stage circuit, one of the following (F1) to (F5):
(F1) a front stage circuit in which both ends of a series unit composed of a pair of capacitors connected in series to each other via a capacitor connection point are respectively connected to the input port P 1 and the input port P 2 , the capacitor connection point being connected to the output port P 4 , and in which a first switch provided between the input port P 1 and the output port P 3 , and a second switch provided between the input port P 2 and the output port P 3 are alternately turned on through switching;
(F2) a front stage circuit including a plurality of units each of which is obtained by interposing a capacitor on a line directly connected to the output port P 3 in the front stage circuit of (F1), the input ports P 1 and P 2 of the plurality of units being connected in series to each other, the output ports P 3 and P 4 of the plurality of units being connected in parallel to each other;
(F3) a front stage circuit in which both ends of a series unit composed of a pair of inductors connected in series to each other via an inductor connection point are respectively connected to the output port P 3 and the output port P 4 , the inductor connection point being connected to the input port P 2 , and in which a first switch provided between the input port P 1 and the output port P 3 , and a second switch provided between the input port P 1 and the output port P 4 are alternately turned on through switching;
(F4) a front stage circuit including a plurality of units each of which is obtained by interposing an inductor on a line directly connected to the input port PI in the front stage circuit of (F3), the input ports PI and P 2 of the plurality of units being connected in parallel to each other, the output ports P 3 and P 4 of the plurality of units being connected in series to each other; and
(F5) a front stage circuit configured to be a full-bridge circuit with four switches so as to receive input through the input ports P 1 and P 2 and perform output through the output ports P 3 and P 4 , and
as the rear stage circuit, one of the following (R1) to (R5):
(R1) a rear stage circuit in which both ends of a series unit composed of a pair of inductors connected in series to each other via an inductor connection point are respectively connected to the input port P 5 and the input port P 6 , the inductor connection point being connected to the output port P 8 , and in which a first switch provided between the input port P 5 and the output port P 7 , and a second switch provided between the input port P 6 and the output port P 7 are alternately turned on through switching;
(R2) a rear stage circuit including a plurality of units each of which is obtained by interposing an inductor on a line directly connected to the output port P 7 in the rear stage circuit of (R1), the input ports P 5 and P 6 of the plurality of units being connected in series to each other, the output ports P 7 and P 8 of the plurality of units being connected in parallel to each other;
(R3) a rear stage circuit in which both ends of a series unit composed of a pair of capacitors connected in series to each other via a capacitor connection point are respectively connected to the output port P 7 and the output port P 8 , the capacitor connection point being connected to the input port P 6 , and in which a first switch provided between the input port P 5 and the output port P 7 , and a second switch provided between the input port P 5 and the output port P 8 are alternately turned on through switching;
(R4) a rear stage circuit including a plurality of units each of which is obtained by interposing a capacitor on a line directly connected to the input port P 5 in the rear stage circuit of (R3), the input ports P 5 and P 6 of the plurality of units being connected in parallel to each other, the output ports P 7 and P 8 of the plurality of units being connected in series to each other; and
(R5) a rear stage circuit configured to be a full-bridge circuit with four switches so as to receive input through the input ports P 5 and P 6 and perform output through the output ports P 7 and P 8 ,
wherein one of the front stage circuits (F1) to (F5) and one of the rear stage circuits (R1) to (R5) are directly combined with each other, excluding a combination that the front stage circuit is (F5) and the rear stage circuit is (R5), to thereby execute simultaneous voltage transformation of AC to AC at the front stage circuit and AC to AC at the rear stage circuit, and a voltage transformation ratio is derived from a combination of the front stage circuit and the rear stage circuit, and,
the voltage transformation is executed irrespective of polarity of AC voltage given from the power supply, and
on-time period of any one of the first switch and the second switch in case of (F1) to (F4) or any two of the switches in case of (F5) in regard to the front stage circuit and
on-time period of any one of the first switch and the second switch in case of (R1) to (R4) or any two of the switches in case of (R5) in regard to the rear stage circuit are synchronized with each other, whereas
there is no time period when both the first switch and the second switch are simultaneously turned on within any one of the front stage circuit and the rear stage circuit.

2. The transformer according to claim 1 , wherein
the series unit is a series unit of a pair of inductors, and
2πf o L<<R<<2πfsL is satisfied,
where f o is a frequency of the power supply, fs is a switching frequency, L is an inductance value of any of the inductors, and R is a resistance value of the load.

3. The transformer according to claim 1 , wherein
the series unit is a series unit of a pair of capacitors, and
1/(2πfsC)<<R<<1/(2πf o C) is satisfied,
where f o is a frequency of the power supply, fs is a switching frequency, C is a capacitance value of any of the capacitors, and R is a resistance value of the load.

4. The transformer according to claim 1 , wherein
in a circuit in which the series unit is provided, a capacitor is interposed on an output line that is not linked to the connection point of the series unit.

5. The transformer according to claim 1 , wherein
a distributed constant circuit is interposed between the front stage circuit and the rear stage circuit, and
in the case where a frequency of output of the front stage circuit is f and a wavelength at the frequency f is λ, the distributed constant circuit includes a first converter with a length of λ/4, and a second converter with a length of λ/4 provided between an end of the first converter and the rear stage circuit.

6. The transformer according to claim 1 , wherein
a two-terminal pair circuit is interposed between the front stage circuit and the rear stage circuit, the two-terminal pair circuit being composed of n-number of reactance elements that are mutually connected, where n is a natural number equal to or greater than 4, and
with respect to any value of a resistance value R of the load, an input impedance Zin of the two-terminal pair circuit has a real number component of k·R, where k is a constant, and an imaginary number component of 0.

7. A tran

Assignees

• Sumitomo Electric Industries
• National Univ Corporation Toyohashi Univ Of Technology

Inventors

• Nakahata Hideaki
• Hirotsu Kenichi
• Shiga Nobuo
• Ohira Takashi
• Yamada Kyohei
• Egashira Daiya

Classifications

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M3/06 Primary

  using resistors or capacitors, e.g. potential divider · CPC title

• H02M5/293 Primary

  using semiconductor devices only · CPC title

• H02M1/0074

  Plural converter units whose inputs are connected in series · CPC title

• H02M5/06

  using impedances · CPC title