Implant regrowth VCSEL and VCSEL array with heterogeneous combination of different VCSEL types

Patent metadata

Field	Value
Publication number	US-10693277-B2
Application number	US-201916533734-A
Country	US
Kind code	B2
Filing date	Aug 6, 2019
Priority date	Sep 28, 2016
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.

First claim

The invention claimed is:

1. A vertical cavity surface emitting laser (VCSEL) comprising:
an active region;
a blocking layer comprising a first material having an implant material, the blocking layer having at least one implant devoid region formed therein extending from a bottom blocking layer surface to a top blocking layer surface, the blocking layer having a first thickness;
each of the at least one implant devoid regions forming a conductive channel in the blocking layer so that the implant material defines a boundary between the blocking layer and each conductive channel that has the first material devoid of the implant material, each conductive channel having:
a bottom conductive channel surface that is continuous with the bottom blocking layer surface,
a top conductive channel surface that is discontinuous with the top blocking layer surface;
a second thickness that is thicker than the first thickness;
a side conductive channel boundary extending from the bottom blocking layer surface to the top blocking layer surface; and
a side conductive channel surface extending from the top blocking layer surface to the top conductive layer surface;

a first non-planarized semiconductor layer over and in contact with the:
top blocking layer surface,
each top conductive channel surface; and
each side conductive channel surface.

2. The VCSEL of claim 1 , wherein the blocking layer and each conductive channel are under the active region, the VCSEL further comprising a plurality of non-planarized semiconductor layers over the first non-planarized semiconductor layer forming a non-planarized semiconductor region with the first non-planarized semiconductor layer.

3. The VCSEL of claim 2 , further comprising a planarized semiconductor layer over the non-planar semiconductor region and under the active region, the planarized semiconductor layer having a planar bottom surface and a planar top surface.

4. The VCSEL of claim 2 , wherein the non-planarized semiconductor region is a mirror period region.

5. The VCSEL of claim 1 , wherein the blocking layer and at least one conductive channel are over the active region, the VCSEL further comprising a plurality of non-planarized semiconductor layers over the first non-planarized semiconductor layer forming a non-planarized semiconductor region with the first non-planarized semiconductor layer.

6. The VCSEL of claim 5 , further comprising a planarized semiconductor layer over the non-planar semiconductor region and having a planar bottom surface and a planar top surface.

7. The VCSEL of claim 5 , wherein the non-planarized semiconductor region is a mirror period region.

8. The VCSEL of claim 1 , further comprising a plurality of the conductive channels laterally arranged with respect to each other in the blocking layer.

9. The VCSEL of claim 1 , wherein the VCSEL is:
devoid of an oxide aperture;
devoid of oxidation; or
devoid of a mesa having the blocking layer and at least one conductive channel.

10. The VCSEL of claim 1 , wherein the implant material is silicon or oxygen.

11. The VCSEL of claim 1 , wherein the first non-planarized semiconductor layer has a connected step such that a lower step on the blocking layer is connected to an upper step above each conductive channel wherein the first non-planarized semiconductor layer has a same material in the lower step and upper step.

12. The VCSEL of claim 1 , wherein the first non-planarized semiconductor layer has a disconnected step such that a lower step on the blocking layer is disconnected to an upper step above each conductive channel, wherein the first non-planarized semiconductor layer has a same material in the lower step and upper step.

13. A vertical cavity surface emitting laser (VCSEL) array comprising:
the VCSEL of claim 1 with a plurality of the conductive channels laterally arranged in a single blocking layer, the plurality of conductive channels being arranged in a pattern.

14. The VCSEL array of claim 13 , wherein the different characteristic is at least one of: different cross-sectional shape; different orientation; different dimension, or divergence angles.

15. The VCSEL array of claim 13 , wherein the pattern is a uniform arrangement of the conductive channels.

16. The VCSEL array of claim 13 , wherein the pattern is a non-uniform arrangement of the conductive channels.

17. The VCSEL array of claim 13 , wherein the pattern is defined by a plurality of sub-patterns of the conductive channels.

18. A method of making the VCSEL of claim 13 , comprising:
forming the layer of the first material;
forming a plurality of resistive layers on the first material to define a cross-sectional profile of a plurality of implant devoid regions;
implanting an implant material into the first material around the plurality of resistive layers to form the blocking layer and define the boundary between the blocking layer and each conductive channel;
etching the blocking layer around the plurality of resistive layers to form the top blocking layer surface and each side conductive channel surface;
removing the plurality of resistive layers to form each top conductive channel surface; and
forming the first non-planarized semiconductor layer over the top blocking layer surface, each top conductive channel surface, and each side conductive channel surface.

19. The VCSEL array of claim 13 , wherein the plurality of conductive channels includes a plurality of different types of conductive channels, each different type of conducive channel having a different characteristic.

20. A method of making the VCSEL of claim 1 , comprising:
forming the layer of the first material;
forming at least one resistive layer on the first material to define a cross-sectional profile of the at least one implant devoid region;
implanting an implant material into the first material around the at least one resistive layer to form the blocking layer and define the boundary between the blocking layer and each conductive channel;
etching the blocking layer around the at least one resistive layer to form the top blocking layer surface and each side conductive channel surface;
removing the at least one resistive layer to form each top conductive channel surface; and
forming the first non-planarized semiconductor layer over the top blocking layer surface, each top conductive channel surface, and each side conductive channel surface.

Assignees

• Finisar Corp
• Ii Vi Delaware Inc

Inventors

• Graham Luke A
• Quadery Sonia
• Gazula Deepa
• Yang Haiquan

Classifications

• H01S5/18308 Primary

  having a special structure for lateral current or light confinement · CPC title

• H01S5/2059

  by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion · CPC title

• H01S5/423

  having a vertical cavity · CPC title

• H01S5/18338

  Non-circular shape of the structure · CPC title

• H01S5/209

  special etch stop layers · CPC title