Thin-film transistor array substrate

Patent metadata

Field	Value
Publication number	US-10692975-B2
Application number	US-201816210934-A
Country	US
Kind code	B2
Filing date	Dec 5, 2018
Priority date	Dec 16, 2014
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A thin-film transistor according to an exemplary embodiment of the present invention comprises an active layer; an intermediate layer; a gate insulating film; a gate electrode; an interlayer insulating film; and source and drain electrodes. The active layer is positioned on a substrate, and the gate insulating film is positioned on the active layer. The gate electrode is positioned on the gate insulating film, and the interlayer insulating film is positioned on the gate electrode. The source and drain electrodes are positioned on the interlayer insulating film and connected to the active layer. The intermediate layer is positioned between the active layer and the gate insulating film, and made of an oxide semiconductor comprising a Group IV element.

First claim

What is claimed is:

1. A thin-film transistor array substrate comprising:
a substrate;
a gate electrode positioned on the substrate;
a gate insulating film positioned on the gate electrode;
an active layer positioned on the gate insulating film;
an etch stopper positioned on the active layer; and
source and drain electrodes positioned on the etch stopper and connected to the active layer,
wherein an intermediate layer made of an oxide semiconductor comprising a Group IV element is positioned between the active layer and the gate insulating film,
wherein the intermediate layer is in contact with a whole surface of one surface of the active layer,
wherein an other surface of the active layer is a surface in contact with a whole surface of one surface of the etch stopper disposed on the other surface of the active layer, and wherein the other surface of the active layer comprises an exposed surface exposed from the etch stopper,
wherein the source and drain electrodes are in contact with the exposed surface, a sidewall of the active layer and a part of an other surface of the etch stopper,
wherein the Group IV element is silicon,
wherein the intermediate layer comprises indium, gallium, and zinc,
wherein a content of the silicon ranges between 2.9×10 22 cm −3 and 3.2×10 22 cm −3 .

2. The thin-film transistor array substrate of claim 1 , wherein the intermediate layer has an atomic ratio of In 0.8 Ga 1 Zn 1 Si 0.5 O (4.2-4.7) .

3. The thin-film transistor array substrate of claim 1 , wherein the intermediate layer has a thickness of 50 to 100 Å.

4. A thin-film transistor array substrate comprising:
a substrate;
a gate electrode positioned on the substrate;
a gate insulating film positioned on the gate electrode;
an active layer positioned on the gate insulating film;
an etch stopper positioned on the active layer; and
source and drain electrodes positioned on the etch stopper and connected to the active layer,
wherein an intermediate layer made of an oxide semiconductor comprising a Group IV element is positioned between the active layer and the gate insulating film,
wherein the intermediate layer is in contact with a whole surface of one surface of the active layer,
wherein an other surface of the active layer is a surface in contact with a whole surface of one surface of the etch stopper disposed on the other surface of the active layer, and wherein the other surface of the active layer comprises an exposed surface exposed from the etch stopper,
wherein the source and drain electrodes are in contact with the exposed surface, a sidewall of the active layer and a part of an other surface of the etch stopper,
wherein the intermediate layer comprises indium, gallium, and zinc,
wherein the Group IV element is silicon,
wherein the intermediate layer further comprises hydrogen, and a content of the hydrogen ranges between 1.2×10 21 cm −3 and 1.6×10 21 cm −3 .

Assignees

• Lg Display Co Ltd

Inventors

• Baeck Juheyuck
• Bae Jonguk
• Oh Saeroonter
• Lee Dohyung
• Park Taeuk

Classifications

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6723

  having light shields · CPC title

• H10D30/6704 Primary

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title